Sami Ajram

Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology

Guy Cathébras, Régis Roubadia, Sami Ajram, 2007, 2007 IEEE International Symposium on Circuits and Systems.

A 50-100 MHz 5 V to -5 V, 1 W Cuk converter using gallium arsenide power switches

Sami Ajram, Georges Salmer, Mamadou Gaye, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs

Guy Cathébras, Régis Roubadia, Sami Ajram, 2006, PATMOS.