Kevin Harer

Learning from Constraints for Formal Property Checking

In-Ho Moon, Kevin Harer, In-Ho Moon, 2009, 2009 IEEE International High Level Design Validation and Test Workshop.

Learning from Constraints for Formal Property Checking

In-Ho Moon, Kevin Harer, 2010, J. Electron. Test..

A robust solution to the timing convergence problem in high-performance design

Narendra V. Shenoy, Kevin Harer, Robert F. Damiano, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Formal methods for coverage analysis of architectural power states in power-managed designs

Ansuman Banerjee, Pallab Dasgupta, Kevin Harer, 2012, 17th Asia and South Pacific Design Automation Conference.

Abstraction-Based Livelock/Deadlock Checking for Hardware Verification

In-Ho Moon, Kevin Harer, In-Ho Moon, 2013, DIFTS@FMCAD.

Supporting sequential assumptions in hybrid verification

Eduard Cerny, Kevin Harer, Pei-Hsin Ho, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Smart simulation using collaborative formal and simulation engines

Jiang Long, Valeria Bertacco, Kevin Harer, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent

Ansuman Banerjee, Subhankar Mukherjee, Pallab Dasgupta, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.