V. Gerousis

New delay model for 0.5/spl mu/ CMOS ASIC

D. Weaver, V. Gerousis, Nghiem Pan, 1993, Sixth Annual IEEE International ASIC Conference and Exhibit.

Track height reduction for standard-cell in below 5nm node: how low can you go?

J. Ryckaert, D. Verkest, P. Raghavan, 2018, Advanced Lithography.

Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs

Sung Kyu Lim, Vassilios Gerousis, Kyungwook Chang, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).