C. Wu

A new interconnection delay model considering the effects of short-channel logic gates

Chung-Yu Wu, M.-C. Shiau, Ming-Chuen Shiau, 1988, 1988., IEEE International Symposium on Circuits and Systems.

Quantization effects in inversion layers of PMOSFETs on Si (100) substrates

K. Sadra, C.-Y. Wu, S. Banerjee, 1996, IEEE Electron Device Letters.

Efficient techniques in the sizing and constrained optimisation of CMOS combinational logic circuits

J.-S. Hwang, C.-Y. Wu, J. Hwang, 1991 .