Marco Lanuzza

发表

Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing

Martin Margala, Marco Lanuzza, Stefania Perri, 2008, PATMOS.

Comparative analysis of yield optimized pulsed flip-flops

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2012, Microelectron. Reliab..

A self-hosting configuration management system to mitigate the impact of Radiation-Induced Multi-Bit Upsets in SRAM-based FPGAs

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2010, 2010 IEEE International Symposium on Industrial Electronics.

Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers

Marco Lanuzza, Felice Crupi, Raffaele De Rose, 2019, 2019 IEEE 13th International Conference on ASIC (ASICON).

Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2016 .

An Embedded System for EEG Acquisition and Processing for Brain Computer Interface Applications

Mario Cannataro, Francesco Amato, Pietro Hiram Guzzi, 2010 .

Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework

Marco Lanuzza, Felice Crupi, Raffaele De Rose, 2019 .

Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions

Angelo Furfaro, Domenico Saccà, Marco Lanuzza, 2019, IDCS.

Evaluation of Dual Mode Logic in 28nm FD-SOI technology

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

Marco Lanuzza, Felice Crupi, Domenico Albano, 2015, Int. J. Circuit Theory Appl..

Low-power split-path data-driven dynamic logic

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2009, IET Circuits Devices Syst..

Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications

Martin Margala, Marco Lanuzza, Pasquale Corsonello, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2009, ARC.

A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications

Martin Margala, Marco Lanuzza, Stefania Perri, 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2007, SAMOS.

Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Low energy/delay overhead level shifter for wide‐range voltage conversion

Sandro Rao, Giuseppe Iannaccone, Marco Lanuzza, 2017, Int. J. Circuit Theory Appl..

Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory

Marco Lanuzza, Felice Crupi, Raffaele De Rose, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs

Marco Lanuzza, Felice Crupi, Raffaele De Rose, 2019, 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations

Marco Lanuzza, Felice Crupi, Raffaele De Rose, 2018, 2018 IEEE 4th International Forum on Research and Technology for Society and Industry (RTSI).

A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops

Marco Lanuzza, 2013, J. Low Power Electron..

Design and evaluation of high-speed energy-aware carry skip adders

Marco Lanuzza, Fabio Frustaci, Raffaele De Rose, 2010, 2010 International Conference on Microelectronics.

A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2020, IEEE Solid-State Circuits Letters.

A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm2 Area in 180nm

Massimo Alioto, Longyang Lin, Marco Lanuzza, 2020, 2020 IEEE Symposium on VLSI Circuits.

Design of high-speed low-power parallel-prefix adder trees in nanometer technologies

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2014, Int. J. Circuit Theory Appl..

Live Demo: An 88fJ / 40 MHz [0.4V] – 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI

Marco Lanuzza, Ramiro Taco, Itamar Levi, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

An Ultralow-Voltage Energy-Efficient Level Shifter

Sandro Rao, Giuseppe Iannaccone, Marco Lanuzza, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 $\times$ 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2019, IEEE Journal of Solid-State Circuits.

Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology

Alexander Fish, Marco Lanuzza, Leonid Yavits, 2020, ISCAS.

A virtual III-V tunnel FET technology platform for ultra-low voltage comparators and level shifters

Marco Lanuzza, Pierpaolo Palestri, Felice Crupi, 2017, 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

Variable precision arithmetic circuits for FPGA-based multimedia processors

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2010, PATMOS.

Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2011 .

Low-Power Level Shifter for Multi-Supply Voltage Designs

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs

Marco Lanuzza, Felice Crupi, Mario Carpentieri, 2017, IEEE Transactions on Electron Devices.

Improving speed and power characteristics of pulse-triggered flip-flops

Marco Lanuzza, Ramiro Taco, 2014, 2014 IEEE 5th Latin American Symposium on Circuits and Systems.

Early assessment of tunnel-FET for energy-efficient logic circuits

Marco Lanuzza, Pierpaolo Palestri, Felice Crupi, 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance

Alexander Fish, Marco Lanuzza, Leonid Yavits, 2020, ISCAS.

Dynamic gate-level body biasing for subthreshold digital design

Marco Lanuzza, Domenico Albano, Ramiro Taco, 2014, 2014 IEEE 5th Latin American Symposium on Circuits and Systems.

Energy-efficient single-clock-cycle binary comparator

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2012, Int. J. Circuit Theory Appl..

Use of skyrmions in the design of multi-level STT-MRAMs

Marco Lanuzza, R. Tomasello, Mario Carpentieri, 2014, MMM 2014.

Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2014, Int. J. Circuit Theory Appl..

Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain

Marco Lanuzza, Pierpaolo Palestri, Felice Crupi, 2015, IEEE Transactions on Electron Devices.

Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

A variation-aware simulation framework for hybrid CMOS/spintronic circuits

Massimo Alioto, Marco Lanuzza, Felice Crupi, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Design of a sub-1-V nanopower CMOS current reference

Marco Lanuzza, Felice Crupi, Raffaele De Rose, 2017, 2017 European Conference on Circuit Theory and Design (ECCTD).

Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems

Martin Margala, Marco Lanuzza, Stefania Perri, 2009, J. Low Power Electron..

New performance/power/area efficient, reliable full adder design

Martin Margala, Marco Lanuzza, Pasquale Corsonello, 2009, GLSVLSI '09.

Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits

Luca Selmi, Marco Lanuzza, Pierpaolo Palestri, 2016, IEEE Transactions on Electron Devices.

Design of a 3T current reference for low-voltage, low-power operation

Giuseppe Iannaccone, Marco Lanuzza, Felice Crupi, 2018, 2018 International Conference on IC Design & Technology (ICICDT).

A high-performance fully reconfigurable FPGA-based 2D convolution processor

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2005, Microprocess. Microsystems.

Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework

Marco Lanuzza, Felice Crupi, Mario Carpentieri, 2017, IEEE Transactions on Nanotechnology.

Design Space Exploration of Split-Path Data Driven Dynamic Full Adder

Martin Margala, Marco Lanuzza, Sohan Purohit, 2010, J. Low Power Electron..

Impact of Random Process Variations on Different 65nm SRAM Cell Topologies

Marco Lanuzza, Pasquale Corsonello, Sumit Kansal, 2010, 2010 3rd International Conference on Emerging Trends in Engineering and Technology.

A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits

Massimo Alioto, Marco Lanuzza, Felice Crupi, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits

Marco Lanuzza, Pierpaolo Palestri, Felice Crupi, 2017 .

Analyzing noise robustness of wide fan-in dynamic logic gates under process variations

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2014, Int. J. Circuit Theory Appl..

Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2010, TRETS.

Low-cost fully reconfigurable data-path for FPGA-based multimedia processor

Martin Margala, Marco Lanuzza, Stefania Perri, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Hardware implementation of a Test Lab for Smart Home environments

Marco Lanuzza, Giuseppe Cocorullo, Carmelo Felicetti, 2015, 2015 AEIT International Annual Conference (AEIT).

Low bit rate image compression core for onboard space applications

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2006, IEEE Transactions on Circuits and Systems for Video Technology.

Design and Implementation of a 90nm Low bit-rate Image Compression Core

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2007 .

Self-repairing SRAM architecture to mitigate the inter-die process variations at 65nm technology

Marco Lanuzza, Pasquale Corsonello, Sumit Kansal, 2011, Microtechnologies.

Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits

Luca Selmi, Marco Lanuzza, Pierpaolo Palestri, 2017, IEEE Transactions on Electron Devices.

A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder

Marco Lanuzza, Fabio Frustaci, 2009, PATMOS.

Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework

Marco Lanuzza, Felice Crupi, Raffaele De Rose, 2020, Integr..

A physical unclonable function based on a 2-transistor subthreshold voltage divider

Marco Lanuzza, Felice Crupi, Raffaele De Rose, 2017, Int. J. Circuit Theory Appl..

A comparative study of MWT architectures by means of numerical simulations

Paolo Magnone, Marco Lanuzza, Felice Crupi, 2013 .

Designing Dynamic Carry Skip Adders: Analysis and Comparison

Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, 2014, Circuits Syst. Signal Process..

A new low-power high-speed single-clock-cycle binary comparator

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath

Martin Margala, Marco Lanuzza, Stefania Perri, 2009, 2009 22nd International Conference on VLSI Design.

Design and Implementation of a 90nm Low bit-rate Image Compression Core

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

A portable class of 3‐transistor current references with low‐power sub‐0.5 V operation

Giuseppe Iannaccone, Marco Lanuzza, Felice Crupi, 2018, Int. J. Circuit Theory Appl..

Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits

Marco Lanuzza, Domenico Albano, Ramiro Taco, 2015, VLSI Design.

Double-precision Dual Mode Logic carry-save multiplier

Marco Lanuzza, Raffaele De Rose, Paul Romero, 2019, Integr..

Impact of Process Variations on Flip-Flops Energy and Timing Characteristics

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design

Marco Lanuzza, Ramiro Taco, Itamar Levi, 2014, 2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI).

Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops

Massimo Alioto, Marco Lanuzza, Felice Crupi, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework

Marco Lanuzza, Felice Crupi, Raffaele De Rose, 2017, 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Designing High-Speed Adders in Power-Constrained Environments

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

STT-MTJ Based Smart Implication for Energy-Efficient Logic-in-Memory Computing

Marco Lanuzza, Felice Crupi, Raffaele De Rose, 2021 .

A Low-Voltage, Low-Power Reconfigurable Current-Mode Softmax Circuit for Analog Neural Networks

Marco Lanuzza, Felice Crupi, Sebastiano Strangio, 2021 .

Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization

Massimo Alioto, Longyang Lin, Marco Lanuzza, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC

Domenico Saccà, Antonino Rullo, Marco Lanuzza, 2021, 2021 IEEE International Conference on Smart Internet of Things (SmartIoT).

Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification pdf

Marco Lanuzza, Leonid Yavits, Adam Teman, 2021, IEEE Access.

A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy

Massimo Alioto, Longyang Lin, Marco Lanuzza, 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC).

A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter

Massimo Alioto, Longyang Lin, Marco Lanuzza, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW

Massimo Alioto, Longyang Lin, Marco Lanuzza, 2021, IEEE Journal of Solid-State Circuits.

Assessment of 2D-FET Based Digital and Analog Circuits on Paper

Giuseppe Iannaccone, Marco Lanuzza, Felice Crupi, 2021 .

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

Marco Lanuzza, Ramiro Taco, Lionel Trojman, 2021, 2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS).

Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET

Alexander Fish, Marco Lanuzza, Ramiro Taco, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies

Marco Lanuzza, Ramiro Taco, Lionel Trojman, 2021, 2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS).

Optimization of rear point contact geometry by means of 3-D numerical simulation

K. Van Wichelen, Enrico Sangiorgi, Claudio Fiegna, 2012 .

Understanding the impact of point-contact scheme and selective emitter in a c-Si BC-BJ solar cell by full 3D numerical simulations

Marco Lanuzza, Felice Crupi, Raffaele De Rose, 2017 .

Design guidelines for a metallization scheme with multiple-emitter contact lines in BC-BJ solar cells

Marco Lanuzza, Felice Crupi, Raffaele De Rose, 2016 .

Opto‐electrical modelling and optimization study of a novel IBC c‐Si solar cell

Marco Lanuzza, Felice Crupi, Raffaele De Rose, 2017 .

Compact Modeling of Perpendicular STT-MTJs With Double Reference Layers

Marco Lanuzza, Felice Crupi, Mario Carpentieri, 2019, IEEE Transactions on Nanotechnology.