Pasquale Corsonello

发表

Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing

Martin Margala, Marco Lanuzza, Stefania Perri, 2008, PATMOS.

Efficient memory architecture for image processing

Stefania Perri, Pasquale Corsonello, 2011, Int. J. Circuit Theory Appl..

Comparative analysis of yield optimized pulsed flip-flops

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2012, Microelectron. Reliab..

A self-hosting configuration management system to mitigate the impact of Radiation-Induced Multi-Bit Upsets in SRAM-based FPGAs

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2010, 2010 IEEE International Symposium on Industrial Electronics.

Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector

Stefania Perri, Pasquale Corsonello, Paolo Zicari, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2020, 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Low-power split-path data-driven dynamic logic

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2009, IET Circuits Devices Syst..

Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications

Martin Margala, Marco Lanuzza, Pasquale Corsonello, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2009, ARC.

Efficient VLSI implementation of statistical carry lookahead adder

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 1998 .

A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications

Martin Margala, Marco Lanuzza, Stefania Perri, 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

Designing Fast Convolutional Engines for Deep Learning Applications

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

64-bit reconfigurable adder for low power media processing

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2002 .

Fast Low-Power 64-Bit Modular Hybrid Adder

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2005, PATMOS.

Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices

Martin Margala, Pasquale Corsonello, Sai Rahul Chalamalasetti, 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

Design of efficient QCA multiplexers

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2016, Int. J. Circuit Theory Appl..

Speed-efficient wide adders for VIRTEX FPGAs

Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, 2002, 9th International Conference on Electronics, Circuits and Systems.

MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2007, SAMOS.

Quad-Port Memory Blocks in Radiation-Tolerant FPGAs: An Application for Image Processing Systems

Pasquale Corsonello, Aakash Jain, Giovanni Staino, 2009, 2009 Second International Conference on Emerging Trends in Engineering & Technology.

An Efficient Convolution Engine based on the À-trous Spatial Pyramid Pooling

Stefania Perri, Pasquale Corsonello, Fanny Spagnolo, 2020, 2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP).

Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2014, IEEE Transactions on Nanotechnology.

Tradeoffs in Digital Binary Adder Design: the effects of floorplanning, number of levels of metals, and supply voltage on performance and area

Stefania Perri, Pasquale Corsonello, Vitit Kantabutra, 2001 .

A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference

Giuseppe Iannaccone, Pasquale Corsonello, Felice Crupi, 2011, IEEE Journal of Solid-State Circuits.

Microprocessor-based FPGA implementation of SPIHT image compression subsystems

Stefania Perri, Pasquale Corsonello, Paolo Zicari, 2005, Microprocess. Microsystems.

Adaptive Census Transform: A novel hardware-oriented stereovision algorithm

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2013, Comput. Vis. Image Underst..

Hybrid carry-select statistical carry look-ahead adder

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 1999 .

Educational design of high-performance arithmetic circuits on FPGA

Pasquale Corsonello, S. Perri, Giuseppe Cocorullo, 1999 .

Design of high-speed low-power parallel-prefix adder trees in nanometer technologies

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2014, Int. J. Circuit Theory Appl..

A low-cost PSoC architecture for long FFT

Pasquale Corsonello, Pietro Angelo Lomoio, 2013, Microtechnologies for the New Millennium.

An integrated countermeasure against differential power analysis for secure smart-cards

Martin Margala, Stefania Perri, Pasquale Corsonello, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory

Rolf Drechsler, Chip-Hong Chang, Chulwoo Kim, 2019, IEEE Trans. Very Large Scale Integr. Syst..

VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits

Stefania Perri, Pasquale Corsonello, Gregorio Cappuccino, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

A matrix product accelerator for field programmable systems on chip

Stefania Perri, Pasquale Corsonello, Paolo Zicari, 2008, Microprocess. Microsystems.

Dynamic power of CMOS gates driving lossy transmission lines

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector

Stefania Perri, Pasquale Corsonello, Paolo Zicari, 2007 .

A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip

Stefania Perri, Pasquale Corsonello, Fanny Spagnolo, 2020 .

Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

SAD-Based Stereo Matching Circuit for FPGAs

Stefania Perri, Pasquale Corsonello, Paolo Zicari, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Power supply noise in accurate delay model for the sub-threshold domain

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2015, Integr..

A high-speed energy-efficient 64-bit reconfigurable binary adder

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2003, IEEE Trans. Very Large Scale Integr. Syst..

VLSI Circuits for Accurate Motion Estimation

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2010, 2010 Third International Conference on Advances in Circuits, Electronics and Micro-electronics.

Variable precision arithmetic circuits for FPGA-based multimedia processors

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2010, PATMOS.

Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2011 .

Low-Power Level Shifter for Multi-Supply Voltage Designs

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator

Stefania Perri, Pasquale Corsonello, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers

Pasquale Corsonello, Fabio Frustaci, Massimo Alioto, 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

Novel Varactor-Loaded Phasing Line for Reflectarray Unit Cell with Large Reconfigurability Frequency Range

Giuseppe Di Massa, Pasquale Corsonello, Francesca Venneri, 2015, WorldCIST.

Embedded surveillance system using background subtraction and Raspberry Pi

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2015, 2015 AEIT International Annual Conference (AEIT).

Editorial

Mark Mohammad Tehranipoor, Meng-Fan Chang, Rajiv V. Joshi, 2017, Formal Aspects of Computing.

Tapered-Vth Approach for Energy-Efficient CMOS Buffers

Massimo Alioto, Pasquale Corsonello, Fabio Frustaci, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

Tapered-Vth Approach for Energy-Efficient

Pasquale Corsonello, Fabio Frustaci, Massimo Alioto, 2011 .

Energy-Efficient Architecture for CNNs Inference on Heterogeneous FPGA

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2019 .

Area- and Power-Reduced Standard-Cell Spanning Tree Adders

Stefania Perri, Pasquale Corsonello, Vitit Kantabutra, 2004, ESA/VLSI.

Analytical Delay Model Considering Variability Effects in Subthreshold Domain

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

Energy-efficient single-clock-cycle binary comparator

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2012, Int. J. Circuit Theory Appl..

VLSI design of low-leakage single-ended 6T SRAM cell

Pasquale Corsonello, F. Frustaci, S. Solanki, 2011, Microtechnologies.

Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2014, Int. J. Circuit Theory Appl..

Efficient addition circuits for Modular design of processors-in-memory

Martin Margala, Stefania Perri, Pasquale Corsonello, 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

Beam-Scanning Reflectarray Based on a Single Varactor-Tuned Element

A. Borgia, Pasquale Corsonello, Sandra Costanzo, 2012 .

LEWIS Project: an integrated system of monitoring, early warning and mitigation of landslides risk

Pasquale Corsonello, Giuseppe Mendicino, G. Di Massa, 2012 .

Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip

Stefania Perri, Pasquale Corsonello, Fanny Spagnolo, 2020, J. Imaging.

An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis

Stefania Perri, Pasquale Corsonello, Fanny Spagnolo, 2019, Sensors.

Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems

Martin Margala, Marco Lanuzza, Stefania Perri, 2009, J. Low Power Electron..

New performance/power/area efficient, reliable full adder design

Martin Margala, Marco Lanuzza, Pasquale Corsonello, 2009, GLSVLSI '09.

Efficient Parallel Circuits for Census Transform

Stefania Perri, Pasquale Corsonello, Daniela Colonna, 2008 .

A high-performance fully reconfigurable FPGA-based 2D convolution processor

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2005, Microprocess. Microsystems.

Efficient absolute difference circuits in Virtex-5 FPGAs

Stefania Perri, Pasquale Corsonello, Paolo Zicari, 2010, Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference.

Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2020, 2020 9th Mediterranean Conference on Embedded Computing (MECO).

Parallel architecture of power-of-two multipliers for FPGAs

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2020, IET Circuits Devices Syst..

Impact of Random Process Variations on Different 65nm SRAM Cell Topologies

Marco Lanuzza, Pasquale Corsonello, Sumit Kansal, 2010, 2010 3rd International Conference on Emerging Trends in Engineering and Technology.

Simd Multipliers for Accelerating Embedded Processors in FPGAS

Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, 2006, J. Circuits Syst. Comput..

A 56-bit self-timed adder for high speed asynchronous datapath

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

Analyzing noise robustness of wide fan-in dynamic logic gates under process variations

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2014, Int. J. Circuit Theory Appl..

An embedded machine vision system for an in-line quality check of assembly processes

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2020, Procedia Manufacturing.

Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2010, TRETS.

Designing high speed asynchronous pipelines

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2000, Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future.

An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs

Stefania Perri, Pasquale Corsonello, Paolo Zicari, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2008, PATMOS.

Low-cost fully reconfigurable data-path for FPGA-based multimedia processor

Martin Margala, Marco Lanuzza, Stefania Perri, 2005, International Conference on Field Programmable Logic and Applications, 2005..

A low-power sub-nanosecond standard-cells based adder

Stefania Perri, Pasquale Corsonello, Giovanni Staino, 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

A sub‐1 V nanopower temperature‐compensated sub‐threshold CMOS voltage reference with 0.065%/V line sensitivity

Giuseppe Iannaccone, Pasquale Corsonello, Felice Crupi, 2015, Int. J. Circuit Theory Appl..

Efficient Approximate Adders for FPGA-Based Data-Paths

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2020 .

Design of Real-Time FPGA-based Embedded System for Stereo Vision

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Power/throughput/area efficient PIM-based reconfigurable array for parallel processing

Martin Margala, Pasquale Corsonello, Sai Rahul Chalamalasetti, 2008, 2008 IEEE International SOC Conference.

Design of a real-time face detection architecture for heterogeneous systems-on-chips

Stefania Perri, Pasquale Corsonello, Fanny Spagnolo, 2020, Integr..

Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

High performance VLSI modules for division and square root

Pasquale Corsonello, Gregorio Cappuccino, Giuseppe Cocorullo, 1998, Microprocess. Microsystems.

Low bit rate image compression core for onboard space applications

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2006, IEEE Transactions on Circuits and Systems for Video Technology.

Design and Implementation of a 90nm Low bit-rate Image Compression Core

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2007 .

Real-time processing of one-bit-coded SAR data

Gilda Schirinzi, Pasquale Corsonello, Gregorio Cappuccino, 1996, Proceedings of 8th Mediterranean Electrotechnical Conference on Industrial Applications in Power Systems, Computer Science and Telecommunications (MELECON 96).

Self-repairing SRAM architecture to mitigate the inter-die process variations at 65nm technology

Marco Lanuzza, Pasquale Corsonello, Sumit Kansal, 2011, Microtechnologies.

Editorial in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Meng-Fan Chang, Rajiv V. Joshi, Naehyuck Chang, 2017 .

A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals

Stefania Perri, Pasquale Corsonello, Paolo Zicari, 2008, Microprocess. Microsystems.

An efficient self-timed adder realized using conventional CMOS standard cells

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2003 .

Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation

Massimo Alioto, Stefania Perri, Pasquale Corsonello, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design of 3:1 multiplexer standard cell

Stefania Perri, Pasquale Corsonello, Vitit Kantabutra, 2000 .

Design and demonstration of a real time processor for one-bit coded SAR signals

Gilda Schirinzi, Pasquale Corsonello, Gregorio Cappuccino, 1996 .

Leakage energy reduction techniques in deep submicron cache memories: a comparative study

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Low-cost FPGA stereo vision system for real time disparity maps calculation

Stefania Perri, Pasquale Corsonello, Paolo Zicari, 2012, Microprocess. Microsystems.

Fast and energy-efficient Manchester carry-bypass adders

Stefania Perri, Pasquale Corsonello, Vitit Kantabutra, 2004 .

Efficient recursive multiply architecture for FPGAs

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2005 .

Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology

Massimo Alioto, Pasquale Corsonello, Fabio Frustaci, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Efficient implementation of cellular algorithms on reconfigurable hardware

Domenico Talia, Giandomenico Spezzano, Pasquale Corsonello, 2002, Proceedings 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing.

Multimodal background subtraction for high-performance embedded systems

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2019, Journal of Real-Time Image Processing.

A new low-power high-speed single-clock-cycle binary comparator

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

An efficient hardware-oriented stereo matching algorithm

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2016, Microprocess. Microsystems.

ESTIMATION OF POWER DISSIPATION FOR TRANSMISSION LINES IN DEEP-SUBMICROMETER ULSI CIRCUITS

Pasquale Corsonello, Giuseppe Cocorullo, Gregorio Cappuccino, 1999 .

Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2003, FPL.

Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath

Martin Margala, Marco Lanuzza, Stefania Perri, 2009, 2009 22nd International Conference on VLSI Design.

Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A novel background subtraction method based on color invariants and grayscale levels

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2014, 2014 International Carnahan Conference on Security Technology (ICCST).

Design and Implementation of a 90nm Low bit-rate Image Compression Core

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

VLSI Implementation of a Low-Power High-Speed Self-Timed Adder

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2000, PATMOS.

High performance square rooting circuit using hybrid radix-2 adders

Stefania Perri, Pasquale Corsonello, 1999 .

Efficient Reconfigurable Manchester Adders for Low-power Media Processing

Stefania Perri, Pasquale Corsonello, 2005, J. Circuits Syst. Comput..

Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs

Stefania Perri, Pasquale Corsonello, Fanny Spagnolo, 2019, 2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME).

Area-Delay Efficient Binary Adders in QCA

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A new high performance circuit for statistical carry lookahead addition

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 1999 .

An Efficient Connected Component Labeling Architecture for Embedded Systems

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2018 .

VLSI implementations of efficient isotropic flexible 2D convolvers

Stefania Perri, Pasquale Corsonello, 2007, IET Circuits Devices Syst..

Fast-squarer circuits using 3-bit-scan without overlapping bits

Stefania Perri, Pasquale Corsonello, 2011, Int. J. Circuit Theory Appl..

VLSI circuits for low-power high-speed asynchronous addition

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Design and demonstration of high throughput square rooting circuit

Pasquale Corsonello, Giuseppe Cocorullo, Gregorio Cappuccino, 1996 .

Impact of Process Variations on Flip-Flops Energy and Timing Characteristics

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Stereo vision architecture for heterogeneous systems-on-chip

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2018, Journal of Real-Time Image Processing.

Design of Efficient BCD Adders in Quantum-Dot Cellular Automata

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation

Stefania Perri, Pasquale Corsonello, Fabio Frustaci, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Designing High-Speed Adders in Power-Constrained Environments

Marco Lanuzza, Stefania Perri, Pasquale Corsonello, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems

Stefania Perri, Pasquale Corsonello, Fanny Spagnolo, 2022, IEEE Access.

Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations

Stefania Perri, Pasquale Corsonello, Fanny Spagnolo, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

CMOS buffer sizing for long on-chip interconnects

Pasquale Corsonello, Giuseppe Cocorullo, Gregorio Cappuccino, 1998 .

High performance mixed-logic asynchronous datapaths with overlapped execution circuits

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, 2000 .

Radial-Shaped Single Varactor-Tuned Phasing Line for Active Reflectarrays

Antonio Raffo, Pasquale Corsonello, Francesca Venneri, 2016, IEEE Transactions on Antennas and Propagation.