Victor Maruri

Interconnect enhancements for a high-speed PLD architecture

Jim Park, Mike Hutton, Rakesh H. Patel, 2002, FPGA '02.

Connection resources for programmable logic integrated circuits

Jim Park, Wei-Jen Huang, Rakesh H. Patel, 2000 .

Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment

Toan Nguyen, Mei Luo, Rakesh H. Patel, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..