Frédéric Bancel

A DFT Technique to Improve ATPG Efficiency for Sequential Circuits

Michel Renovell, Yves Bertrand, Frédéric Bancel, 1993, The Sixth International Conference on VLSI Design.

Robustness of circuits under delay-induced faults : test of AES with the PAFI tool

Assia Tria, Laurent Freund, Frédéric Bancel, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

Secure scan techniques: a comparison

Bruno Rouzeyre, Marie-Lise Flottes, David Hély, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

Test control for secure scan designs

Bruno Rouzeyre, Marie-Lise Flottes, David Hély, 2005, European Test Symposium (ETS'05).

Multiconfiguration technique to reduce test duration for sequential circuits

Michel Renovell, Yves Bertrand, Frédéric Bancel, 1993, Proceedings of IEEE International Test Conference - (ITC).

Securing Scan Control in Crypto Chips

Bruno Rouzeyre, Marie-Lise Flottes, David Hély, 2007, J. Electron. Test..

Securing embedded programmable gate arrays in secure circuits

Lionel Torres, Gilles Sassatelli, Frédéric Bancel, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

Integration of Reconfigurable Logic on Secure Circuits

Lionel Torres, Frédéric Bancel, Nicolas Valette, 2005, ReCoSoC.

Communication management method between an electronic device, for example a card contactless chip and a communication apparatus, for example a reader, and corresponding electronic device

Frédéric Bancel, Nathalie Link, Brigitte Hennebois, 2010 .

Scan Design and Secure Chip

Michel Renovell, Bruno Rouzeyre, Marie-Lise Flottes, 2004, IOLTS.

A secure Scan Design Methodology

Bruno Rouzeyre, Marie-Lise Flottes, David Hély, 2006, Proceedings of the Design Automation & Test in Europe Conference.