J.-Y. Jou

A JOINT PROJECT TO DEVELOP A VLSI TESTING AND DESIGN-FOR-TESTABILITY COURSE FOR UNIVERSITIES IN TAIWAN

Kuen-Jong Lee, Cheng-Wen Wu, C.-L. Lee, 1997 .

Efficient coverage analysis metric for HDL design validation

J.-Y. Jou, C.-N. Liu, Jing-Yang Jou, 2001 .

Power-oriented partial-scan design approach

J.-Y. Jou, M.-C. Nien, 1998 .

A testable PLA design with low overhead and ease of test generation

J.-Y. Jou, 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.