Il-soo Lee

Using the nonlinear property of FSR and dictionary coding for reduction of test volume

Jae-Hoon Jeong, Anthony P. Ambler, Il-soo Lee, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

Reduction of power and test time by removing cluster of don't-care from test data set

Anthony P. Ambler, Yu-Ting Lin, Il-soo Lee, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

Two efficient methods to reduce power and testing time

Tony Ambler, Il-soo Lee, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint

Baxter F. Womack, Geewhun Seok, Tony Ambler, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

The efficient multiple scan chain architecture reducing power dissipation and test time

Yong Min Hur, Tony Ambler, Il-soo Lee, 2004, 13th Asian Test Symposium.

Reduction of Input Test Data and Power based on Analysis of Deterministic Test Input and its Test Response

Yong Min Hur, Il-soo Lee, Yongmin Hur, 2004 .