T. Iwata

A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme

A. Matsuzawa, H. Yamauchi, H. Akamatsu, 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

A low power data holding circuit with an intermittent power supply scheme for sub-1V MT-CMOS LSIs

A. Matsuzawa, H. Yamauchi, H. Yamamoto, 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

Quantification of shrinkage deformation on line-heating

T. Iwata, K. Matsuoka, 2003 .

A 5 Gbps CMOS frequency tolerant multi phase clock recovery circuit

T. Iwata, H. Kimura, T. Yoshikawa, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

Gate-over-driving CMOS architecture for 0.5 V single-power-supply-operated devices

A. Matsuzawa, H. Akamatsu, H. Yamauchi, 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.