Y. K. Seng

1.1 V full-swing double bootstrapped BiCMOS logic gates

S. S. Rofail, Y. K. Seng, 1996 .

Novel low-voltage BiCMOS digital circuits employing a lateral p-n-p BJT in a p-MOS structure

S. S. Rofail, Y. K. Seng, S. Rofail, 1996 .

Delay time sensitivity analysis of multi-generation BiCMOS digital circuits

S. S. Rofail, Y. K. Seng, S. Y. Seng, 1997 .

Full-swing high speed CBiCMOS digital circuit for low-voltage applications

S. S. Rofail, Y. K. Seng, 1995 .

New current conveyor for high-speed low-power current sensing

Y. K. Seng, 1998 .

Design and analysis of a ±1V CMOS four-quadrant analogue multiplier

S. S. Rofail, Y. K. Seng, 1998 .

Altering transistor positions: impact on the performance and power dissipation of dynamic latches and flip-flops

S. S. Rofail, Y. K. Seng, S. M. Mishra, 1999 .

Design and analysis of a /spl plusmn/1 V CMOS four-quadrant analogue multiplier

S. S. Rofail, Y. K. Seng, 1998 .

1.5 V high-speed electrostatic discharge free BiCMOS digital circuit

Y. K. Seng, S. Rofail, 1998 .

1.5 V high speed low power CMOS current sense amplifier

S. S. Rofail, Y. K. Seng, 1995 .

A new active polyphase filter for wideband image reject downconverter

Yeo Kiat Seng, Do Manh Anh, Y. K. Seng, 2002, ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575).

A 3–8 GHz Low-Noise CMOS Amplifier

Yeo Kiat Seng, Y. K. Seng, A. Meaamar, 2009, IEEE Microwave and Wireless Components Letters.

PCMOS-based Hardware Implementation of Bayesian Network

Goh Wang Ling, Zhang Weijia, Yeo Kiat Seng, 2007, 2007 IEEE Conference on Electron Devices and Solid-State Circuits.