Soo-Ik Chae

发表

Implementation of an OpenVG Rasterizer with Configurable Anti-Aliasing and Multi-Window Scissoring

Ren Huang, Soo-Ik Chae, 2006, The Sixth IEEE International Conference on Computer and Information Technology (CIT'06).

Discrete-time cellular neural networks using distributed arithmetic

Soo-Ik Chae, Sunjung Park, Joonho Lim, 1995 .

ybrid Approach for Improving iscri~inati~n i Recognition

Soo-Ik Chae, 2009 .

A single-chip 2.4 GHz direct-conversion CMOS transceiver with GFSK modem for Bluetooth application

Deog-Kyoon Jeong, Kang-Yoon Lee, Wonchan Kim, 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

Template-Set Approach to VLSI Pattern Inspection

Chong-Cheng Fu, James D. Meindl, Soo-Ik Chae, 1987, Other Conferences.

Fast vector quantizer using multiple sorted index tables

Soo-Ik Chae, Sun-Young Choi, 1996, Proceedings of 3rd IEEE International Conference on Image Processing.

Improved sufficient convergence condition for the discrete-time cellular neural networks

Soo-Ik Chae, Sungjun Park, 1997, Proceedings of International Conference on Neural Networks (ICNN'97).

A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment

Soo-Ik Chae, Sanggyu Park, Sang-yong Yoon, 2006, Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06).

Microstore - The Stanford Analog Memory Unit

Soo-Ik Chae, J. T. Walker, S. Shapiro, 1985, IEEE Transactions on Nuclear Science.

Defect Detection And Classification Using The Euler Number

Chong-Cheng Fu, Soo-Ik Chae, R. Fabian Pease, 1988, Advanced Lithography.

New motion estimation using low-resolution quantization for MPEG2 video encoding

Seongsoo Lee, Soo-Ik Chae, Jeong-Min Kim, 1996, VLSI Signal Processing, IX.

A hardware operating system kernel for multi-processor systems

Soo-Ik Chae, Sanggyu Park, Do-sun Hong, 2008, IEICE Electron. Express.

An Integrated Cycle-Accurate Energy Measurement Circuit for CMOS VLSI Systems

Soo-Ik Chae, Eunseok Song, Soon Kwon, 2004 .

New MPEG2 decoder architecture using frequency scaling

Soo-Ik Chae, Jeong-Min Kim, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

A Cycle-Accurate Energy Estimator for CMOS Digital Circuits

Soon Kwon, Soo-Ik Chae, Eunseok Song, 2004, PATMOS.

Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation

Luigi Carro, Ahmed Amine Jerraya, Lei Li, 2009, Integr..

Digit Recognition with Slant Regularization

Soo-Ik Chae, Eel Wan Lee, 1994 .

A Programmable Video Platform and Its Application Mapping Framework Using the Target Application's SystemC Models

Soo-Ik Chae, Daewoong Kim, Kilhyung Cha, 2011, EURASIP J. Embed. Syst..

A three-port nRERL register file for ultra-low-energy applications

Soo-Ik Chae, Joonho Lim, Jun-Ho Kwon, 2000, ISLPED '00.

Ratio pulse arithmetic for radial basis function network

Soo-Ik Chae, Joonho Lim, 1995, Proceedings of ICNN'95 - International Conference on Neural Networks.

Functional modeling techniques for efficient SW code generation of video codec applications

Ahmed Amine Jerraya, Soo-Ik Chae, Sang-Il Han, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Modified probabilistic RAM architecture for VLSI implementation of a backpropagation learning algorithm

Soo-Ik Chae, Eel-Wan Lee, Jae-Hee Won, 1993, 1993 IEEE International Symposium on Circuits and Systems.

Region-growing approach to detect microcalcifications in digital mammograms

Soo-Ik Chae, Dong-Sun Park, Jin-wook Shin, 2001, International Symposium on Multispectral Image Processing and Pattern Recognition.

Emulator environment based on an FPGA prototyping board

Soo-Ik Chae, Sangyong Yoon, Kyung-Soo Oh, 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).

Simple reversible energy recovery logic using NMOS switch networks with cross-coupled PMOS pair

Soo-Ik Chae, Kipaek Kwon, 1998 .

A Backpropagation Algorithm for Neural Networks Using Random Pulse Streams

Soo-Ik Chae, JeungWon Suh, 1992 .

Motion estimation algorithm using low resolution quantisation

Soo-Ik Chae, Seongsoo Lee, 1996 .

GPD training of the state weighting functions in hidden control neural network

Soo-Ik Chae, Kyungmin Na, 1996, 1996 IEEE International Conference on Acoustics, Speech, and Signal Processing Conference Proceedings.

A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems

Soo-Ik Chae, Joonho Lim, Dong-Gyu Kim, 1999 .

Buffer memory optimization for video codec application modeled in Simulink

Ahmed Amine Jerraya, Soo-Ik Chae, Xavier Guerin, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Corrective training of hidden control neural network

Souguil Ann, Soo-Ik Chae, Kyungmin Na, 1995, Proceedings of ICNN'95 - International Conference on Neural Networks.

Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks

Soo-Ik Chae, Daewoong Kim, Kilhyung Cha, 2009, 2009 IEEE Workshop on Signal Processing Systems.

Frequency-domain implementation of block adaptive filters for ICA-based multichannel blind deconvolution+I3055

Soo-Ik Chae, Kyungmin Na, Kyungjin Lee, 1999 .

A Bootstrapped Switch for nMOS Reversible Energy Recovery Logic for Low-Voltage Applications

Soo-Ik Chae, Seokkee Kim, 2006, IEICE Trans. Electron..

A study on the stochastic computation using the ratio of one pulses and zero pulses

Soo-Ik Chae, Seung-Jai Min, Eel-Wan Lee, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Digital implementation of discrete-time cellular neural networks with distributed arithmetic

Soo-Ik Chae, Sungjun Park, Joonho Lim, 1997, Proceedings of International Conference on Neural Networks (ICNN'97).

New Perceptron Model Using Random Bitstreams

Soo-Ik Chae, Eel-Wan Lee, 1995, Neural Computation.

IMPLEMENTATION OF THE RECONFIGURABLE DISCRETE-TIME CELLULAR NEURAL NETWORKS

Soo-Ik Chae, Sung Jun Park, Joon Ho Lim, 1995 .

Complexity reduction in an nRERL microprocessor

Soo-Ik Chae, Seokkee Kim, S. Chae, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Adaptive Scanline Filling Algorithm for OpenVG 2D Vector Graphics Accelerator

Soo-Ik Chae, Daewoong Kim, Kilhyung Cha, 2009, IEICE Trans. Inf. Syst..

Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage

Takayasu Sakurai, Soo-Ik Chae, Koichi Nose, 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

RTL generation of channel architecture templates for a template-based SoC design flow

Soo-Ik Chae, Jinhyun Cho, Soonwoo Choi, 2008, 2008 Forum on Specification, Verification and Design Languages.

Fast Design of Reduced-Complexity Nearest-Neighbor Classifiers Using Triangular Inequality

Soo-Ik Chae, Eel-Wan Lee, 1998, IEEE Trans. Pattern Anal. Mach. Intell..

Storage system for analog data.

Soo-Ik Chae, James T. Walker, Stephen L. Shapiro, 1985 .

Efficient test bitstream generation method for verification of HEVC decoders

Soo-Ik Chae, Dosun Hong, 2014, The 18th IEEE International Symposium on Consumer Electronics (ISCE 2014).

Single-sensor active noise cancellation using recurrent neural network predictors

Soo-Ik Chae, Kyungmin Na, S. Chae, 1997, Proceedings of International Conference on Neural Networks (ICNN'97).

Generation of efficient bitstreams for functional tests of video decoders

Soo-Ik Chae, Soonwoo Choi, Seunggyu Jeoung, 2013, 2013 IEEE International Conference on Consumer Electronics (ICCE).

An 8/spl times/8-b nRERL serial multiplier for ultra-low-power applications

Soo-Ik Chae, Joonho Lim, Dong-G. Kim, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

An 8×8 nRERL serial multiplier for ultra-low-power aplications

Soo-Ik Chae, Joonho Lim, Dong-G. Kim, 2000, ASP-DAC '00.

A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264

Minho Kim, Soo-Ik Chae, Ingu Hwang, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

A High-Performance Videophone Chip with Dual Multimedia VLIW Processor Cores

Soo-Ik Chae, Jeong-Min Kim, Sang-Il Han, 2001 .

A VLSI DESIGN OF THE NEURAL NETWORKS USING RANDOM PULSE STREAMS

Soo-Ik Chae, Sung Jun Park, Cheon Gon Kim, 1992 .

Coding efficiency of AVS 2.0 for CBAC and CABAC engines

Youngkyu Choi, Soo-Ik Chae, Jing Cui, 2015, International Conference on Machine Vision.

an optimized rendering algorithm for hardware implementation of openVG 2D vector graphics

Soo-Ik Chae, Daewoong Kim, Kilhyung Cha, 2008, 2008 International SoC Design Conference.

Content-addressable memory for VLSI pattern inspection

Chong-Cheng Fu, Soo-Ik Chae, Roger Fabian W. Pease, 1988 .

An HMM/MLP hybrid approach for improving discrimination in speech recognition

Soo-Ik Chae, Kyungmin Na, 1998, 1998 IEEE International Joint Conference on Neural Networks Proceedings. IEEE World Congress on Computational Intelligence (Cat. No.98CH36227).

An adaptive hash-based search for integer motion estimation in SCC

Hyuk-Jae Lee, Youngkyu Choi, Soo-Ik Chae, 2019, IEICE Electron. Express.

Partial bus-invert coding for power optimization of system level bus

Kiyoung Choi, Soo-Ik Chae, Youngsoo Shin, 1998, ISLPED '98.

A reset-free anti-harmonic delay-locked loop using a cycle period detector

Soo-Ik Chae, Jeong-Woo Lee, Joonbae Park, 2004 .

Two-step motion estimation algorithm using low-resolution quantization

Seongsoo Lee, Soo-Ik Chae, 1996, Proceedings of 3rd IEEE International Conference on Image Processing.

VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications

Soo-Ik Chae, Doowon Lee, Sanggyu Park, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 2 GHz CMOS double conversion downconverter with robust image rejection performance against the process and temperature variations

Wonchan Kim, Soo-Ik Chae, Eunseok Song, 2000 .

Multithread video coding processor for the videophone

Soo-Ik Chae, Jeong-Min Kim, Eel-Wan Lee, 1995, VLSI Signal Processing, VIII.

Template-Set Approach to VLSI (Very Large Scale Integrated) Pattern Inspection,

Chong-Cheng Fu, James D. Meindl, Soo-Ik Chae, 1984 .

A Hybrid Verification Methodology for SoCBase-DE Design Flow

Soo-Ik Chae, Jin-Hyun Cho, Doowon Lee, 2007 .

New classifier with reduced computational complexity

Soo-Ik Chae, Eel-Wan Lee, 1995, Proceedings of ICNN'95 - International Conference on Neural Networks.

Frequency-domain separation of convolved non-stationary signals with adaptive non-causal FIR filters

Soo-Ik Chae, Kyung Jin Lee, Kyungmin Na, 2000, 2000 10th European Signal Processing Conference.

Maskable associative memory design for VLSI pattern inspection

Chong-Cheng Fu, Soo-Ik Chae, James T. Walker, 1987, 1987 Symposium on VLSI Circuits.

Cache Optimization for H.264/AVC Motion Compensation

Soo-Ik Chae, Sang-yong Yoon, 2008, IEICE Trans. Inf. Syst..

Reduction of bus transitions with partial bus-invert coding

Kiyoung Choi, Soo-Ik Chae, Youngsoo Shin, 1998 .

New Motion Estimation Algorithm and Its Block-Matching Criteria Using Low-Resolution Quantization

Soo-Ik Chae, Seong Soo Lee, S. Chae, 1998 .

Flexible DMA subsystem in multi-core platforms for video applications

Soo-Ik Chae, Moonmo Koo, 2010, IEICE Electron. Express.

An Alternative RPT Neuron Model : Introducing a Nonlinearity into RPT Neuron Model

Soo-Ik Chae, Eel Wan Lee, 1992 .

Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264

Luigi Carro, Ahmed Amine Jerraya, Lei Li, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Discriminative training of hidden Markov models using overall risk criterion and reduced gradient method

Souguil Ann, Soo-Ik Chae, Dong-Il Chang, 1995, EUROSPEECH.

An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory

Amer Baghdadi, Ahmed Amine Jerraya, Soo-Ik Chae, 2004, Proceedings. 41st Design Automation Conference, 2004..

Neural network implementation using new pulse arithmetic

Soo-Ik Chae, Seung-Jai Min, 1994 .

POWER-BUS NOISE CONTROL FOR HIGH-SPEED CMOS VLSI CIRCUITS

Soo-Ik Chae, 1989 .

Decoding of main 4:2:2 10-bit bitstreams in HEVC Main 8-bit best-effort decoders

Hyunmin Jung, Soo-Ik Chae, Woo Seok Jeong, 2016, 2016 IEEE International Conference on Consumer Electronics (ICCE).

A high-performance OpenVG accelerator with dual-scanline filling rendering

Soo-Ik Chae, Daewoong Kim, Kilhyung Cha, 2008, IEEE Transactions on Consumer Electronics.

Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC

Luigi Carro, Ahmed Amine Jerraya, Ricardo Reis, 2007, Des. Autom. Embed. Syst..

Coding efficiency of the context-based arithmetic coding engine of AVS 2.0 in the HEVC encoder

Hyunmin Jung, Soo-Ik Chae, Soonwoo Choi, 2015, 2015 IEEE International Conference on Consumer Electronics (ICCE).

Character recognition by neural networks with single-layer training and rejection mechanism

Soo-Ik Chae, Joonho Lim, Eel-Wan Lee, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264

Minho Kim, Soo-Ik Chae, Ingu Hwang, 2005, ASP-DAC '05.

Gradual refinement for application-specific MPSoC design from Simulink model to RTL implementation

Luigi Carro, Ahmed Amine Jerraya, Xiaolang Yan, 2009 .

Error Analysis in the Digital Implementation Using Random Pulse Train

Soo-Ik Chae, Jeung Won Suh, 1991 .

Fast Integer Motion Estimation With Bottom-Up Motion Vector Prediction for an HEVC Encoder

Hyuk-Jae Lee, Chae Eun Rhee, Soo-Ik Chae, 2018, IEEE Transactions on Circuits and Systems for Video Technology.

An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design

Kiyoung Choi, Sungjoo Yoo, Soo-Ik Chae, 2003, Des. Autom. Embed. Syst..

A two-week program for a platform-based SoC design

Soo-Ik Chae, Sanggyu Park, 2005, 2005 IEEE International Conference on Microelectronic Systems Education (MSE'05).

Session details: System level architecture design

Soo-Ik Chae, Sreedhar Natarrajan, 2005, ASP-DAC '05.

New motion estimation algorithm using adaptively quantized low bit-resolution image and its VLSI architecture for MPEG2 video encoding

Seongsoo Lee, Soo-Ik Chae, Jeong-Min Kim, 1998, IEEE Trans. Circuits Syst. Video Technol..

Partial bus-invert coding for power optimization of application-specific systems

Kiyoung Choi, Soo-Ik Chae, Youngsoo Shin, 2001, IEEE Trans. Very Large Scale Integr. Syst..

A cycle-accurate joulemeter for CMOS VLSI circuits

In-Chan Choi, Soo-Ik Chae, Eunseok Song, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

Next-Generation Memory [Guest editors' introduction]

Greg Atwood, Soo-Ik Chae, Simon S.Y. Shim, 2013, Computer.

A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor

Soo-Ik Chae, Daewoong Kim, Soonwoo Choi, 2010, 23rd IEEE International SOC Conference.

Template-Set Approach to Defect Detection and Classification for VLSI Patterns,

Chong-Cheng Fu, Soo-Ik Chae, Roger Fabian W. Pease, 1986 .

An 8-b nRERL microprocessor for ultra-low-energy applications

Soo-Ik Chae, Jun-Ho Kwon, Seokkee Kim, 2001, ASP-DAC '01.

Reusable component IP design using refinement-based design environment

Soo-Ik Chae, Sanggyu Park, Sang-yong Yoon, 2006, Asia and South Pacific Conference on Design Automation, 2006..

A C/C++-based functional verification framework using the SystemC verification library

Soo-Ik Chae, Sanggyu Park, 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).

High performance IPC hardware accelerator and communication network for MPSoCs

Soo-Ik Chae, Moonmo Koo, 2008, 2008 International SoC Design Conference.

A 0.25-/spl mu/m CMOS quad-band GSM RF transceiver using an efficient LO frequency plan

Yeon-Jae Jung, Soo-Ik Chae, Eunseok Song, 2005 .

Stereo correspondence with discrete-time cellular neural networks

Soo-Ik Chae, Seung-Jai Min, Sungjun Park, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

An OpenVG-Compliant Vector Graphics Accelerator

Ren Huang, Soo-Ik Chae, 2006 .

A mixed-level virtual prototyping environment for SystemC-based design methodology

Soo-Ik Chae, Sanggyu Park, Sang-yong Yoon, 2009, Microelectron. J..

Hardware implementation of inter-processor communication in MPSoCs for multimedia applications

Soo-Ik Chae, Moonmo Koo, 2007 .

Recurrent neural prediction models for speech recognition

Souguil Ann, Soo-Ik Chae, Dong-Il Chang, 1995, EUROSPEECH.

Reduction in energy consumption by bootstrapped nMOS switches in reversible adiabatic CMOS circuits

Soo-Ik Chae, Dong-Gyu Kim, Junho Lim, 1999 .

Implementation of a simple 8-bit microprocessor with reversible energy recovery logic

Soo-Ik Chae, Seokkee Kim, 2005, CF '05.

Constrained-random bitstream generation for H.264/AVC decoder conformance test

Soo-Ik Chae, Jinhyun Cho, Soonwoo Choi, 2010, IEEE Transactions on Consumer Electronics.

A modified TZ search algorithm for parallel integer motion estimation in high efficiency video coding

Hyuk-Jae Lee, Soo-Ik Chae, Tae Sung Kim, 2015, 2015 International SoC Design Conference (ISOCC).

A cost-effective architecture for HDTV video decoder in ATSC receivers

Soo-Ik Chae, Jeong-Min Kim, 1998 .

Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC

Luigi Carro, Ahmed Amine Jerraya, Ricardo Reis, 2007, SCOPES '07.

nMOS reversible energy recovery logic for ultra-low-energy applications

Soo-Ik Chae, Joonho Lim, Dong-Gyu Kim, 2000, IEEE Journal of Solid-State Circuits.

High Throughput CBAC Hardware Encoder With Bin Merging for AVS 2.0 Video Coding

Hyuk-Jae Lee, Soo-Ik Chae, Young-Kyu Choi, 2021, IEEE Transactions on Circuits and Systems for Video Technology.

Simple binary wavelet filters for efficient VLSI implementation

Soo-Ik Chae, A. M. Rassau, K. Eshraghian, 1999 .

Partial bus-invert coding for power optimization of system level bus

Kiyoung Choi, Soo-Ik Chae, Youngsoo Shin, 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

Serial Multiplier for ultra-low-power applications

Soo-Ik Chae, Joonho Lim, Dong-Gyu Kim, 1999 .

A fast fractional motion estimation algorithm for high efficiency video coding

Hyuk-Jae Lee, Young-Kyu Choi, Soo-Ik Chae, 2016, 2016 International Conference on Electronics, Information, and Communications (ICEIC).

Comparison of CABAC rate estimation models for HEVC rate distortion optimisation

Soo-Ik Chae, Soonwoo Choi, 2014 .

Modified delta coding algorithm for real parameter optimisation

Souguil Ann, Soo-Ik Chae, Kyungmin Na, 1995 .