David Ho

Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications

Vempati Srinivasa Rao, C. T. Chong, Chai Tai Chong, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

FOWLP design for HBM applications

Surya Bhattacharya, David Ho, Lim Teck Guan, 2017, 2017 IEEE 19th Electronics Packaging Technology Conference (EPTC).

Thin-Film Magnetic Inductors on Silicon for Integrated Power Converters

Don Disney, Ravinder Pal Singh, Lulu Peng, 2020, IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society.

Assembly of large dies fine pitch Cu/low-k FCBGA package with through silicon via (TSV) interposer

David Ho, Leong Ching Wai, D. Pinjala, 2009, 2009 11th Electronics Packaging Technology Conference.

Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging

F. X. Che, David Ho, Mian Zhi Ding, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Underfill characterization for multi-layer 3D-SiP stacked chip package

David Ho, Ser Choong Chong, V. S. Rao, 2011, 2011 IEEE 13th Electronics Packaging Technology Conference.

Modeling and design solutions to overcome warpage challenge for fan-out wafer level packaging (FO-WLP) technology

F. X. Che, David Ho, Mian Zhi Ding, 2015, 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC).

Integrated Magnetic Inductor Technology on Silicon

Salahuddin Raju, Serine Soh, David Ho, 2018, 2018 IEEE 20th Electronics Packaging Technology Conference (EPTC).