Yansheng Luo

Simulation of interconnect inductive impact in the presence of process variations in 90 nm and beyond

Xiaoning Qi, A. Gyure, Yansheng Luo, 2006, IEEE Electron Device Letters.

Measurement and Simulation of Interconnect Inductance in 90 nm and Beyond

Xiaoning Qi, A. Gyure, Yansheng Luo, 2005, 2005 International Conference On Simulation of Semiconductor Processes and Devices.

Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies

Kishore Singhal, Xiaoning Qi, Alex Gyure, 2006, GLSVLSI '06.

A statistical method for fast and accurate capacitance extraction in the presence of floating dummy fills

Shabbir H. Batterywala, Alex Gyure, Yansheng Luo, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

A New Simulation Method for NBTI Analysis in SPICE Environment

Yu Cao, Kishore Singhal, Xiaoning Qi, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations

Kishore Singhal, Xiaoning Qi, Alex Gyure, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..