S.C. Lo

Simulation of interconnect inductive impact in the presence of process variations in 90 nm and beyond

Xiaoning Qi, A. Gyure, Yansheng Luo, 2006, IEEE Electron Device Letters.

Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries

A. Gyure, S.C. Lo, M. Shahram, 2006, IEEE Circuits and Devices Magazine.

Measurement and Simulation of Interconnect Inductance in 90 nm and Beyond

Xiaoning Qi, A. Gyure, Yansheng Luo, 2005, 2005 International Conference On Simulation of Semiconductor Processes and Devices.