K. Singhal

Simulation of interconnect inductive impact in the presence of process variations in 90 nm and beyond

Xiaoning Qi, A. Gyure, Yansheng Luo, 2006, IEEE Electron Device Letters.

A signal integrity-driven buffer insertion technique for post-routing noise and delay optimization

D. E. Long, C. Ortiz, K. Singhal, 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

Statistical device models from worst case files and electrical test data

V. Visvanathan, K. Singhal, V. Visvanathan, 1999 .

Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries

A. Gyure, S.C. Lo, M. Shahram, 2006, IEEE Circuits and Devices Magazine.

Measurement and Simulation of Interconnect Inductance in 90 nm and Beyond

Xiaoning Qi, A. Gyure, Yansheng Luo, 2005, 2005 International Conference On Simulation of Semiconductor Processes and Devices.

Intrinsic MOSFET capacitance coefficients

K. Singhal, H. K. Gummel, 2001 .

Predictive worst case statistical modeling of 0.8- mu m BICMOS bipolar transistors: a methodology based on process and mixed device/circuit level simulators

I. C. Kizilyalli, M. J. Thoma, K. Singhal, 1993 .

A consistent nonisothermal extension of the Scharfetter—Gummel stable difference approximation

K. Singhal, E.L. Heasell, C.C. McAndrew, 1985, IEEE Electron Device Letters.