M. Mouis

发表

Fully Depleted SOI MOSFETs with WSix metal gate on HfO2 gate dielectric

M. Vinet, D. Lafond, S. Deleonibus, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Experimental gate misalignment analysis on double gate SOI MOSFETs

M. Vinet, S. Deleonibus, J. Widiez, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

FMNT - Federation on Micro Nano Technologies Grenoble Exposé invité

M. Mouis, 2009 .

TiN metal gate thickness influence on fully depleted SOI MOSFETs physical and electrical properties

M. Vinet, S. Deleonibus, J. Widiez, 2005, 2005 IEEE International SOI Conference Proceedings.

VLSI integration of SiGe epitaxial base bipolar transistors

A. Chantre, M. Mouis, A. Chantre, 1998, 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167).

Evaluation of strain-induced mobility variation in TiN metal gate SOI n-MOSFETs

M. Vinet, S. Deleonibus, M. Mouis, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

Scaling prospects in mechanical energy harvesting using piezoelectric nanostructures

R. Hinchet, G. Ardila, M. Mouis, 2012, 2012 International Semiconductor Conference Dresden-Grenoble (ISCDG).

Monte Carlo study of apparent mobility reduction in nano-MOSFETs

A. Bournel, G. Ghibaudo, S. Galdin-Retailleau, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Electrical transport characterization of nano CMOS devices with ultra-thin silicon film

G. Ghibaudo, G. Bidal, S. Cristoloveanu, 2009, 2009 International Workshop on Junction Technology.

A 54 GHz f/sub max/ implanted base 0.35 /spl mu/m single-polysilicon bipolar technology

O. Rozeau, G. Auvert, L. Ailloud, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Experimental Comparison Between Sub-0.1-$\mu{\hbox{m}}$ Ultrathin SOI Single- and Double-Gate MOSFETs: Performance and Mobility

M. Vinet, S. Deleonibus, J. Widiez, 2006, IEEE Transactions on Nanotechnology.

Experimental Evidence of Mobility Enhancement in Short-Channel Ultra-thin Body Double-Gate MOSFETs

G. Ghibaudo, M. Vinet, S. Deleonibus, 2006, 2006 European Solid-State Device Research Conference.

Performance Optimization of Vertical Nanowire‐based Piezoelectric Nanogenerators

Gustavo Ardila, Laurent Montès, M. Mouis, 2013 .

Optimisation of a Link Base Implant for Reducing the Access Base Resistance of Single-Poly Quasi Self-Aligned Bipolar Transistors

M. Laurens, L. Vendrame, A. Chantre, 1996, ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference.

Scaling rules of piezoelectric nanowires in view of sensor and energy harvester integration

R. Hinchet, G. Ardila, M. Mouis, 2012, 2012 International Electron Devices Meeting.

Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length

X. Garros, J. Mazurier, O. Faynot, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance

M. Vinet, S. Deleonibus, J. Widiez, 2005, IEEE Transactions on Electron Devices.

Low temperature characterization of 14nm FDSOI CMOS devices

G. Ghibaudo, A. Cros, M. Mouis, 2014, 2014 11th International Workshop on Low Temperature Electronics (WOLTE).

Accurate Determination of Transport Parameters in Sub‐65 nm MOS Transistors

G. Ghibaudo, M. Mouis, 2013 .

Demonstration of Enhanced Base Diffusion Due to Extrinsic Base Implantations in Submicron, Polysilicon-Emitter, Epitaxial Base Bipolar Transistors

S. Denorme, A. Chantre, M. Mouis, 1995, ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference.

Electron mobility enhancement in uniaxially strained MOSFETs: Extraction of the effective mass variation

G. Reimbold, D. Blachier, M. Casse, 2006, 2006 European Solid-State Device Research Conference.

Mechanical simulation of stress engineering solutions in highly strained p-type FDSOI MOSFETs for 14-nm node and beyond

O. Rozeau, J. Lacord, L. Grenouillet, 2015, 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Three-Dimensional Real-Space Simulation of Surface Roughness in Silicon Nanowire FETs

M. Mouis, M. Mouis, M. Pala, 2009, IEEE Transactions on Electron Devices.