Javier Olivito

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array

Javier Resano, Hortensia Mecha, Juan Antonio Clemente, 2018, IET Comput. Digit. Tech..

Accelerating Board Games Through Hardware/Software Codesign

Javier Resano, José Luis Briz, Javier Olivito, 2017, IEEE Transactions on Computational Intelligence and AI in Games.

An improved FPGA-based specific processor for Blokus Duo

Alberto Delmas, Javier Resano, Javier Olivito, 2014, 2014 International Conference on Field-Programmable Technology (FPT).

An Efficient Hardware Accelerator to Handle Compressed Filters and Avoid Useless Operations in CNNs

Javier Resano, Javier Olivito, Adrián Alcolea Moreno, 2018 .

Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems

Javier Resano, Hortensia Mecha, Javier Olivito, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors

Carlos González, Javier Resano, Ruben Gran Tejero, 2015, Microprocess. Microsystems.

An FPGA-based specific processor for Blokus Duo

Carlos González, Javier Resano, Javier Olivito, 2013, 2013 International Conference on Field-Programmable Technology (FPT).

FPGA implementation of a strong Reversi player

Carlos González, Javier Resano, Javier Olivito, 2010, 2010 International Conference on Field-Programmable Technology.