H. Van Tran

A 2.5 V 256-level non-volatile analog storage device using EEPROM technology

H. Van Tran, T. Blyth, D. Sowards, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

Vertical floating-gate 4.5F/sup 2/ split-gate NOR flash memory at 110nm node

Feng Gao, S.Y. Chang, V. Huang, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..