Natsuki Kushiyama

A 12 MHz data cycle 4 Mb DRAM with pipeline operation

T. Furuyama, Yohji Watanabe, Kazuyoshi Muraoka, 1991 .

A 500Megabyte/s Data-Rate 4.5M DRAM (Special Section on the 1992 VLSI Circuits Symposium)

Mark Horowitz, Kiyofumi Sakurai, Hiroyuki Noji, 1993 .

An experimental 295 MHz CMOS 4K/spl times/256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers

Natsuki Kushiyama, C. Tan, R. Clark, 1995 .

Wafer burn-in (WBI) technology for RAM's

T. Furuyama, T. Yoshida, Natsuki Kushiyama, 1993, Proceedings of IEEE International Electron Devices Meeting.

A 295 MHz CMOS 1 M (/spl times/256) embedded SRAM using bi-directional read/write shared sense amps and self-timed pulsed word-line drivers

Natsuki Kushiyama, R. Clark, L. Martin, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

500 Mbyte/sec data-rate 512 Kbits*9 DRAM using a novel I/O interface

Victor E. Lee, Kiyofumi Sakurai, Mark Horowitz, 1992, 1992 Symposium on VLSI Circuits Digest of Technical Papers.

A 500-megabyte/s data-rate 4.5 M DRAM

Victor E. Lee, Kiyofumi Sakurai, Mark Horowitz, 1993 .

FP 18.3: A 295MHz CMOS 1 M (~2%) Embedded SMM using Bidirectional ReaWrite Shared Sense Amps and Self-Timed Pulsed Word-Line Driven

Natsuki Kushiyama, Richard Clark, Charles Tan, 1993 .

A 60-ns 4-Mbit CMOS DRAM with built-in selftest function

Kenji Natori, T. Furuyama, Takashi Ohsawa, 1987 .