Hoeju Chung

8Gb 3D DDR3 DRAM using through-silicon-via technology

So-Ra Kim, Hoon Lee, Tae-Kyung Jung, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

Ki-Whan Song, Young-Hyun Jun, Jaewhan Kim, 2011, 2011 IEEE International Solid-State Circuits Conference.

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel

Jung Sunwoo, Young-Chan Jang, Yun-Sang Lee, 2009, IEEE Journal of Solid-State Circuits.

Channel BER Measurement for a 5.8Gb/s/pin unidirectional differential I/O for DRAM application

Jung Sunwoo, Yun-Sang Lee, Sang-Yun Kim, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

Young-Hyun Jun, Dukha Park, Sooho Cha, 2009, IEEE Journal of Solid-State Circuits.

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

Hyoung-Joo Kim, Jong-Ho Lee, Jun-Young Park, 2015, IEEE Journal of Solid-State Circuits.

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

Qi Wang, Jaewhan Kim, Jinyoung Kim, 2012, 2012 IEEE International Solid-State Circuits Conference.

SCR-based ESD protection for high bandwidth DRAMs

Ki-Whan Song, Yeong-Taek Lee, Changhyun Kim, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

Hyoung-Joo Kim, Kiwon Lee, Joon-Young Park, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

HBM3 RAS: Enhancing Resilience at Scale

Sudhanva Gurumurthi, Kyomin Sohn, Vilas Sridharan, 2021, IEEE Computer Architecture Letters.