A. Agarwal

Fabrication of high Ge content SiGe layer on Si by Ge condensation technique

S. Balakumar, G. Lo, D. Kwong, 2006, 2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

A process technique to engineer the stress of thick doped polysilicon films for MEMS applications

J. Singh, R. Nagarajan, A. Agarwal, 2002, Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614).

Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance

S.C. Rustagi, N. Balasubramanian, N. Singh, 2006, 2006 International Electron Devices Meeting.