Jae Sung Sim

Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation

Il Han Park, Ki-Whan Song, Byung-Gook Park, 2006 .

A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology

Chilhee Chung, Byung-Gook Park, Jong Duk Lee, 2004 .

Reliability Characteristics of TANOS (TaN/AlO/SiN/Oxide/Si)NAND Flash Memory with Rounded Corner (RC) Structure

Juhyung Kim, Chang-Hyun Lee, Sanghun Jeon, 2008, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design.

Observation and Effective Suppression of Dielectric Relaxation in Charge-Trap NAND Flash Memory

Chilhee Chung, Jeong-Hyuk Choi, Jungdal Choi, 2011, 2011 3rd IEEE International Memory Workshop (IMW).

SET/CMOS hybrid process and multiband filtering circuits

Ki-Whan Song, Young-Wug Kim, Yong Kyu Lee, 2005 .

Intrinsic fluctuations in Vertical NAND flash memories

Chilhee Chung, Keun-Ho Lee, Young-Kwan Park, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Self Aligned Trap-Shallow Trench Isolation Scheme for the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory

Sanghun Jeon, Jungdal Choi, Jae Sung Sim, 2007, 2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop.

Realistic single-electron transistor modeling and novel CMOS/SET hybrid circuits

Ki-Whan Song, Byung-Gook Park, Jong Duk Lee, 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..

Multilevel Data Storage Memory Devices Based on the Controlled Capacitive Coupling of Trapped Electrons

Jae Sung Sim, Quanxi Jia, Byeong-Hyeok Sohn, 2011, Advanced materials.