T. Hamamoto

A Floating Body Cell (FBC) fully Compatible with 90nm CMOS Technology Node for Embedded Applications

Atsushi Sakamoto, Akihiro Nitayama, Takashi Ohsawa, 2006, 2006 IEEE International Conference on IC Design and Technology.

An experimental DRAM with a NAND-structured cell

F. Masuoka, S. Shiratake, D. Takashima, 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Well concentration: a novel scaling limitation factor derived from DRAM retention time and its modeling

Takeshi Hamamoto, S. Sugiura, S. Sawada, 1995, Proceedings of International Electron Devices Meeting.

An 18.5ns 128MB SOI DRAM with a floating body cell

Takashi Ohsawa, Shigeyoshi Watanabe, Takeshi Hamamoto, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility

Akihiro Nitayama, Takashi Ohsawa, K. Inoh, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Scaling scenario of floating body cell (FBC) suppressing Vth variation due to random dopant fluctuation

Akihiro Nitayama, Ryo Fukuda, Takashi Ohsawa, 2008, 2008 IEEE International SOI Conference.