Hiroyuki Yotsuyanagi

发表

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs

Widianto, Masaki Hashizume, Shohei Suenaga, 2016, IEICE Trans. Inf. Syst..

Testability analysis of IDDQ testing with large threshold value

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

Test pattern for supply current test of open defects by applying time-variable electric field

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Output voltage estimation of a floating interconnect line caused by a hard open in 90nm ICs

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2010, 2010 10th International Symposium on Communications and Information Technologies.

Electric field for detecting open leads in CMOS logic circuits by supply current testing

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement

Kozo Kinoshita, Hiroyuki Yotsuyanagi, Seiji Kajihara, 1995, IEICE Trans. Inf. Syst..

I/sub DDQ/ test method based on wavelet transformation for noisy current measurement environment

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2004, 13th Asian Test Symposium.

On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection

Masaki Hashizume, Hiroyuki Yotsuyanagi, Toshiaki Satoh, 2019, 2019 International 3D Systems Integration Conference (3DIC).

Fault-Aware Dependability Enhancement Techniques for Flash Memories

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fault Analysis of Interconnect Opens in 90nm CMOS ICs with Device Simulator

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2008 .

A built-in supply current test circuit for pin opens in assembled PCBs

Masaki Hashizume, Hiroyuki Yotsuyanagi, Shoichi Umezu, 2014, 2014 International Conference on Electronics Packaging (ICEP).

Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2017 .

Stand-by Mode Test Method of Interconnects between Dies in 3D ICs with IEEE 1149.1 Test Circuits

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2018, 2018 IEEE CPMT Symposium Japan (ICSJ).

Power supply circuit for high speed operation of adiabatic dynamic CMOS logic circuits

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

Test time reduction for I/sub DDQ/ testing by arranging test vectors

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2015, 2015 International 3D Systems Integration Conference (3DIC).

A test circuit for pin shorts generating oscillation in CMOS logic circuits

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2004, Systems and Computers in Japan.

SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops

Masaki Hashizume, Hiroyuki Yotsuyanagi, Masayuki Yamamoto, 2010, IEICE Trans. Inf. Syst..

Undetectable fault removal of sequential circuits based on unreachable states

Kozo Kinoshita, Hiroyuki Yotsuyanagi, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

A supply current testable register string DAC of decoder type

Yutaka Hata, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2011, 2011 11th International Symposium on Communications & Information Technologies (ISCIT).

CMOS open defect detection by supply current test

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

New Class of Tests for Open Faults with Considering Adjacent Lines

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2009, 2009 Asian Test Symposium.

Synthesis of Sequential Circuits by Redundancy Removal and Retiming

Kozo Kinoshita, Hiroyuki Yotsuyanagi, Seiji Kajihara, 1997, J. Electron. Test..

Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

Current Testable Design of Resistor String DACs

Yutaka Hata, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2007 .

Electrical interconnect test method of 3D ICs by injected charge volume

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2015, 2015 International 3D Systems Integration Conference (3DIC).

Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

Applied AC Voltage for Detecting Open Leads of CMOS LSI by Monitoring Supply Current under AC Electric Field

Masaki Hashizume, Hiroyuki Yotsuyanagi, Masao Takagi, 2007 .

Modified PRPG for Test Data Reduction Using BAST Structure

Masaki Hashizume, Hiroyuki Yotsuyanagi, Zheng Hong Cai, 2017 .

Synthesis for testability by sequential redundancy removal using retiming

Kozo Kinoshita, Hiroyuki Yotsuyanagi, Seiji Kajihara, 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.

A BUILT-IN TEST CIRCUIT FOR DETECTING OPEN INTERCONNECTS IN 3D ICS

Masaki Hashizume, Hiroyuki Yotsuyanagi, Widianto Widianto, 2018 .

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, 2013, IEICE Trans. Inf. Syst..

CMOS open defect detection based on supply current in time-variable electric field and supply voltage application

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2001, Proceedings 10th Asian Test Symposium.

A built-in electrical test circuit for detecting open leads in assembled PCB circuits

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2016, 2016 International Conference on Electronics Packaging (ICEP).

Identification of feedback bridging faults with oscillation

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2013, 2013 22nd Asian Test Symposium.

Reduction method of number of electromagnetic simulation times for estimating output voltage at hard open TSV in 3D IC

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2013, 2013 3rd IEEE CPMT Symposium Japan.

On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVs

Masaki Hashizume, Hiroyuki Yotsuyanagi, Akihiro Fujiwara, 2015, 2015 International 3D Systems Integration Conference (3DIC).

Reducing scan shifts using folding scan trees

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2003, 2003 Test Symposium.

CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2002 .

A study on multiple path selection conditions in delay testing using design-for-testability circuit

Masaki Hashizume, Hiroyuki Yotsuyanagi, Ryosuke Mori, 2015 .

A testable design for electrical interconnect tests of 3D ICs

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2015, 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference (ICEP-IAAC).

Built-in IDDT appearance time sensor for detecting open faults in 3D IC

Shyue-Kung Lu, Masaki Hashizume, Shohei Suenaga, 2013, 2013 3rd IEEE CPMT Symposium Japan.

Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code

Masaki Hashizume, Hiroyuki Yotsuyanagi, Masashi Ishikawa, 2010, 2010 19th IEEE Asian Test Symposium.

Random pattern testability of the open defect detection method using application of time-variable electric field

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

A Redundancy Removal Method for Sequential Circuits Based on Unreachable States

Kozo Kinoshita, Hiroyuki Yotsuyanagi, Seiji Kajihara, 1998 .

On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2017, 2017 17th International Symposium on Communications and Information Technologies (ISCIT).

Test Sequence Generation for Test Time Reduction of IDDQ Testing

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2004, IEICE Trans. Inf. Syst..

Electrical interconnect test method of 3D ICs without boundary scan flip flops

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2015, 2015 IEEE CPMT Symposium Japan (ICSJ).

Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2002 .

Electrical test method of open defects at data buses in 3D SRAM IC

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2014, 2014 International Conference on Electronics Packaging (ICEP).

Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2019, 2019 International 3D Systems Integration Conference (3DIC).

A built-in current sensor made of a comparator of offset cancellation type for electrical interconnect tests of 3D ICs

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2017, 2017 IEEE CPMT Symposium Japan (ICSJ).

Testability for resistive open defects by electrical interconnect test of 3D ICs without boundary scan flip flops

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2016, 2016 IEEE CPMT Symposium Japan (ICSJ).

Open Lead Detection Based on Logical Change Caused by AC Voltage Signal Stimulus

Masaki Hashizume, Hiroyuki Yotsuyanagi, Masao Takagi, 2008 .

DFT for supply current testing to detect open defects at interconnects in 3D ICs

Shyue-Kung Lu, Masaki Hashizume, Shohei Suenaga, 2013, 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS).

Statistical Supply Current Test Method for Opens in TTL Circuits with IC Characteristics Variations

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2005 .

A test circuit for pin shorts generating oscillation in CMOS logic circuits

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2004 .

Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2004, IEICE Trans. Inf. Syst..

Preliminary Analysis of Interconnect Full Open Faults using TEG chips

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2009 .

Testability of Pin Open in Small Outline Package ICs by Supply Current Test

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2003 .

Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2003 .

Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture

Masaki Hashizume, Hiroyuki Yotsuyanagi, Tomoaki Konishi, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

A built-in supply current test circuit for electrical interconnect tests of 3D ICs

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2014, 2014 International 3D Systems Integration Conference (3DIC).

A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2017, 2017 17th International Symposium on Communications and Information Technologies (ISCIT).

A power supply circuit recycling charge in adiabatic dynamic CMOS logic circuits

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

Extraction of Fault Candidate Areas with Layout Information

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2004 .

Trends in 3D Integrated Circuit (3D-IC) Testing Technology

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2015 .

Sequential redundancy removal using test generation and multiple unreachable states

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2001, Proceedings 10th Asian Test Symposium.

Repair Circuit of TSVs in a 3D Stacked Memory IC

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2015 .

A BIST Circuit for IDDQ Tests

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2003 .

Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design

Masaki Hashizume, Hiroyuki Yotsuyanagi, Satoshi Hirai, 2018, 2018 IEEE 27th Asian Test Symposium (ATS).

A method for diagnosing resistive open faults with considering adjacent lines

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2010, 2010 10th International Symposium on Communications and Information Technologies.

A built-in test circuit for open defects at interconnects between dies in 3D ICs

Widianto, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

CMOS open fault detection by appearance time of switching supply current

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

Pin Open Detection for CMOS Logic ICs by Measuring Supply Current under AC Electric Field

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2003 .

I/sub DDQ/ sensing technique for high speed IDDQ testing

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2001, Proceedings 10th Asian Test Symposium.

Pin open detection of BGA IC by supply current testing

Masaki Hashizume, Hiroyuki Yotsuyanagi, Akira Ono, 2014, 2014 International Conference on Electronics Packaging (ICEP).

Bi-directional of a Built-in Test Circuit for Interconnect Defects in Assembled PCBs

Masaki Hashizume, Hiroyuki Yotsuyanagi, Lailis Syafaah, 2017 .

High speed IDDQ test and its testability for process variation

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2000, Proceedings of the Ninth Asian Test Symposium.

Current testable design of resistor string DACs

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2006, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06).

On configuring scan trees to reduce scan shifts based on a circuit structure

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

Current-based testable design of level shifters in liquid crystal display drivers

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2010, 2010 15th IEEE European Test Symposium.

A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification

Masayuki Arai, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, 2011, 2011 Asian Test Symposium.

Threshold value estimation of electrical interconnect tests with scan FFs

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2014, IEEE CPMT Symposium Japan 2014.

IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2002 .

A Supply Current Test Method for Bridging Faults in CMOS Microprocessor Based Circuits

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2003 .

A Novel Approach for Improving the Quality of Open Fault Diagnosis

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2009, 2009 22nd International Conference on VLSI Design.

Oscillation Frequency Estimation for Detecting Feedback Bridging Faults

Hiroyuki Yotsuyanagi, Takeomi Tamesada, Massaki Hashizume, 2002 .

A power supply circuit for interconnect tests based on injected charge volume of 3D IC

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2016, 2016 IEEE CPMT Symposium Japan (ICSJ).

A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2017, 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Testability of Supply Current Test in an AGC Circuit

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2003 .

Resynthesis for sequential circuits designed with a specified initial state

Kozo Kinoshita, Hiroyuki Yotsuyanagi, Seiji Kajihara, 1995, Proceedings 13th IEEE VLSI Test Symposium.

A BIST circuit for I/sub DDQ/ tests

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2003, 2003 Test Symposium.

Electrical Test for Open Defects in CMOS ICs by Injected Charge

Masaki Hashizume, Hiroyuki Yotsuyanagi, Daisuke Suga, 2015 .

Current Testable Design of Resistor String DACs for Short Defects

Yutaka Hata, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2008 .

A built-in defective level monitor of resistive open defects in 3D ICs with logic gates

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2016, 2016 IEEE CPMT Symposium Japan (ICSJ).

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2009, 2009 22nd International Conference on VLSI Design.

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2018, IEICE Trans. Inf. Syst..

A Built-In Test Circuit for Detecting Open Defects by IDDT Appearance Time in CMOS ICs

Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, 2015 .

Improving the Diagnostic Quality of Open Faults

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2008 .

A built-in test circuit for supply current testing of open defects at interconnects in 3D ICs

Masaki Hashizume, Hiroyuki Yotsuyanagi, Tomoaki Konishi, 2012, 2012 4th Electronic System-Integration Technology Conference.

On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC

Masaki Hashizume, Hiroyuki Yotsuyanagi, Shuya Kikuchi, 2019, 2019 IEEE International Test Conference in Asia (ITC-Asia).

Practical fault coverage of supply current tests for bipolar ICs

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

Feasibility of IDDQ Tests for Shorts in Deep Submicron ICs

Masaki Hashizume, Hiroyuki Yotsuyanagi, Isao Tsukimoto, 2009 .

Propagation Delay Analysis of a Soft Open Defect inside a TSV

Masaki Hashizume, Hiroyuki Yotsuyanagi, M. Hashizume, 2011 .

Lead Open Detection Based on Supply Current of CMOS LSIs

Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 2004 .