Rudolf Schlangen

发表

Development and Evaluation of Novel Chip Modification- and Analysis-Techniques, based on Backside Focused Ion Beam Preparation

Rudolf Schlangen, 2010 .

Non destructive 3D chip inspection with nano scale potential by use of backside FIB and backscattered electron microscopy

Rudolf Schlangen, Christian Boit, Uwe Kerst, 2007, Microelectron. Reliab..

Backside E-Beam Probing on Nano scale devices

Rudolf Schlangen, Christian Boit, Uwe Kerst, 2007, 2007 IEEE International Test Conference.

Dynamic lock-in thermography for operation mode-dependent thermally active fault localization

Rudolf Schlangen, S. Li, K. Yu, 2010, Microelectron. Reliab..

Electrical Performance Evaluation of FIB Edited Circuits through Chip Backside Exposing Shallow Trench Isolations

Rudolf Schlangen, Christian Boit, Uwe Kerst, 2005, Microelectron. Reliab..

Physical analysis, trimming and editing of nanoscale IC function with backside FIB processing

Rudolf Schlangen, Christian Boit, Uwe Kerst, 2009, Microelectron. Reliab..

Contact to contacts or silicide by use of backside FIB circuit edit allowing to approach every active circuit node

Rudolf Schlangen, Christian Boit, Uwe Kerst, 2006, Microelectron. Reliab..

Focused ion beam contact to non-volatile memory cells

Rudolf Schlangen, Christian Boit, Clemens Helfmeier, 2014, Microelectron. Reliab..

Through Package Defect Localization by Lock-In Thermography

Rudolf Schlangen, Herve Deslandes, Toru Toda, 2011 .

Impact of back side circuit edit on active device performance in bulk silicon ICs

Rudolf Schlangen, Uwe Kerst, Ted Lundquist, 2005, IEEE International Conference on Test, 2005..

Physical Techniques for Chip-Backside IC Debug in Nanotechnologies

Rudolf Schlangen, Christian Boit, Uwe Kerst, 2008, IEEE Design & Test of Computers.

RF performance increase allowing IC timing adjustments by use of backside FIB processing

Rudolf Schlangen, C. Boit, Ted Lundquist, 2009, 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Non-destructive defect depth determination at fully packaged and stacked die devices using Lock-in Thermography

Rudolf Schlangen, Frank Altmann, Herve Deslandes, 2010, 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Use of Lock-In Thermography for N onD estructive 3 D Defect Localization on System in Package and Stacked-Die Technology

Rudolf Schlangen, Frank Altmann, F. Altmann, 2011 .

Physical IC debug – backside approach and nanoscale challenge

Rudolf Schlangen, Christian Boit, Steven Kasapi, 2008 .

Lock-in Thermography for Flip-Chip Package Failure Analysis

Rudolf Schlangen, Kannu Wadhwa, Lihong Cao, 2012 .