Alain Greiner

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A high performance modular embedded ROM architecture

Marcello Duhalde, Alain Greiner, Frédéric Pétrot, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Early Power Estimation in Heterogeneous Designs Using SoCLib and SystemC-AMS

Alain Greiner, François Pêcheux, Khouloud Zine el Abidine, 2010, PATMOS.

THE MPC PARALLEL COMPUTER : HARDWARE, LOW-LEVEL PROTOCOLS AND PERFORMANCES

Alain Greiner, Amal Zerrouki, Olivier Gluck, 2000 .

Analyse Temporelle des Circuits VLSI à Haute Densité d'Intégration Utilisant des Technologies Submicroniques

Alain Greiner, Karim Dioury, Marie-Minerve Rosset-Louërat, 1997 .

Automatic Translation of SystemC Simulation Model From VHDL RTL Model : a Semantic Approach

Alain Greiner, Richard Buchmann, 2006 .

Interactive Learning of Processor Architecture

Alain Greiner, François Dromard, Yves Body, 1999 .

NOE : A PROGRAMMABLE NETWORK CONTROLLER

Alain Greiner, Amal Zerrouki, Cyril Spasevski, 2001 .

An Example of Practice Based Engineering Education : the Design of a Microprogrammed MIPS Processor with the Alliance CAD System

Alain Greiner, Marie-Martine Paget, Pirouz Bazargan Sabet, 2001 .

Exploiting Large Memory Using 32-Bit Energy-Efficient Manycore Architectures

Quentin L. Meunier, Alain Greiner, Franck Wajsbürt, 2016, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC).

Support matériel à l'exécution multi-threads pour le processeur Mips R3000 : Micro-Architecture et caractérisation

Alain Greiner, Boris Boutillier, Laurent Mortiez, 2002 .

TAS: an accurate timing analyser for CMOS VLSI

Alain Greiner, Amjad Hajjar, Roland Marbot, 1991, Proceedings of the European Conference on Design Automation..

SmartHSL : An Evaluation Board for the IEEE 1355 Technology.

Alain Greiner, Alexandre Fenyö, Jean-Jacques Lecler, 1997 .

La machine MPC

Alain Greiner, Pierre David, Alexandre Fenyö, 1998 .

Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations

Alain Greiner, François Pêcheux, Aline Mello, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCs

Alain Greiner, François Pêcheux, Nicolas Pouillon, 2009, 2009 IEEE/IFIP International Symposium on Rapid System Prototyping.

RWT: Suppressing Write-Through Cost When Coherence is Not Needed

Quentin L. Meunier, Alain Greiner, Hao Liu, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures

Alain Greiner, Mounir Benabdenbi, Zhen Zhang, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Two efficient synchronous <--> asynchronous converters well-suited for networks-on-chip in GALS architectures

Alain Greiner, Abbas Sheibanyrad, 2008, Integr..

An Integrated PCI Component for IEEE 1355

Alain Greiner, Cyril Spasevski, Franck Wajsbürt, 1997 .

STESI: a new software-based strategy for testing socs containing wrapped IP cores

Alain Greiner, Mounir Benabdenbi, Matthieu Tuna, 2005 .

Parallel TLM simulation of MPSoC on SMP workstations: Influence of communication locality

Alain Greiner, Francois Pecheux, Isaac Maia Pessoa, 2010, 2010 International Conference on Microelectronics.

Un Algorithme de Routage Reconfigurable pour la Tolérance aux Fautes dans le micro-réseau DSPIN

Alain Greiner, Zhen Zhang, 2008 .

Estimating Energy Consumption for an MPSoC Architectural Exploration

Jean-Luc Dekeyser, Alain Greiner, Samy Meftali, 2006, ARCS.

Accurate static timing analysis for deep submicronic CMOS circuits

Alain Greiner, Karim Dioury, Marie-Minerve Rosset-Louërat, 1997 .

Using C to write portable CMOS VLSI module generators

Alain Greiner, Frédéric Pétrot, A. Greiner, 1994, EURO-DAC '94.

A Scalable Architecture for System-on-Chip Interconnections

Alain Greiner, Pierre Guerrier, Pierre Guerrier, 1999 .

A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

Alain Greiner, Ivan Miro Panades, Abbas Sheibanyrad, 2006, 2006 1st International Conference on Nano-Networks and Workshops.

Using VCI in a on-chip system around SPIN network

Alain Greiner, Laurent Mortiez, Emmanuelle Encrenaz, 2004 .

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters

Christian Bernard, Fabien Clermidy, Alain Greiner, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Design of a high complexity superscalar microprocessor with the portable IDPS ASIC library

Alain Greiner, L. Lucas, Franck Wajsbürt, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

DESB, a functional abstractor for CMOS VLSI circuits

Alain Greiner, Roland Marbot, M. Laurentin, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

Physical design of the VCI wrappers for the on-chip packet-switched network named SPIN

Alain Greiner, Adrijean Andriahantenaina, Hervé Charlery, 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..

Application of a redefinable symbolic simulation technique in VLSI testability design rules checking

Alain Greiner, Mokhtar Hirech, El Housseine Rejouan, 1994, 27th Annual Simulation Symposium.

A simulation environment for core based embedded systems

Alain Greiner, Frédéric Pétrot, Denis Hommais, 1997, Proceedings of 1997 SCS Simulation Multiconference.

RCube: a message routing device using the OMI/HIC high speed link technology

Alain Greiner, Frédéric Potter, A. Derieux, 1996, Proceedings of Third International Conference on Electronics, Circuits, and Systems.

GECOS : Mécanisme de synchronisation passant à l'échelle à plusieurs lecteurs et un écrivain pour structures chaînées

Quentin L. Meunier, Alain Greiner, Franck Wajsbürt, 2015, Tech. Sci. Informatiques.

FITPATH: A Process-Independent Datapath Compiler Providing High Density Layout

Alain Greiner, Lotfi Ben Ammar, 1992, Synthesis for Control Dominated Circuits.

Physical design of the VCI wrappers for the on-chip packet-switched network named SPIN

Alain Greiner, Herve Charlery, Adrijean Andriahantenaina, 2004 .

Automated Hierarchical Knowledge-Based Synthesis for Analog Cells using CAIRO+

Alain Greiner, Ramy Iskander, Marie-Minerve Louerat, 2006 .

Architectural exploration of a fine-grained 3D cache for high performance in a manycore context

Alain Greiner, Ivan Miro Panades, Eric Guthmuller, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches

Quentin L. Meunier, Alain Greiner, Ivan Miro Panades, 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC).

A Language to Design Generators of Analog Functions

Alain Greiner, Marie-Minerve Rosset-Louërat, Vincent Bourguet, 2004 .

The influence of system calls and interrupts on the performance of a PC cluster using a remote DMA communication primitive

Alain Greiner, Jean-Luc Lamotte, Olivier Glück, 2002 .

A redefinable symbolic simulation technique for testability design rules checking

Alain Greiner, Mokhtar Hirech, El Housseine Rejouan, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester

Alain Greiner, Mounir Benabdenbi, Matthieu Tuna, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

FSM synthesis on FPGA architectures

Alain Greiner, E. P. Lopes, G. Sarwary, 1994, Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit.

Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture

Fabien Clermidy, Alain Greiner, Ivan Miro Panades, 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

A generic hardware / software communication middleware for streaming applications on shared memory multi processor systems-on-chip

Alain Greiner, Etienne Faure, Daniela Genius, 2009, 2009 Forum on Specification & Design Languages (FDL).

Hybrid-Timing FIFOs to Use on Networks-on-Chip in GALS Architectures

Alain Greiner, Abbas Sheibanyrad, 2007, ESA.

Fault-Tolerance Mechanisms for Permanent Failures in a Coherent Shared-Memory Many-Core Architecture

Alain Greiner, César Fuguet, 2014 .

CAIRO : A hierarchical layout language for analog circuits

Alain Greiner, Marie-Minerve Rosset-Louërat, Mohamed Dessouky, 1999 .

An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles

Alain Greiner, François Pêcheux, Emmanuel Viaud, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture

Alain Greiner, Ivan Miro Panades, Abbas Sheibanyrad, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure

Alain Greiner, Mounir Benabdenbi, Zhen Zhang, 2011, 29th VLSI Test Symposium.

Micro-network for SoC: implementation of a 32-port SPIN network

Alain Greiner, Adrijean Andriahantenaina, A. Greiner, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management

Christian Bernard, Fabien Clermidy, Alain Greiner, 2021, IEEE Journal of Solid-State Circuits.

Synthèse de Circuits Analogiques CMOS

Alain Greiner, Marie-Minerve Rosset-Louërat, Mohamed Dessouky, 1998 .

Conception d’un microprocesseur de quatre bits: de la spécification à la réalisation

Alain Greiner, Amara Amara, Anne Derieux, 1991 .

MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation

Alain Greiner, Mounir Benabdenbi, Raphaël Labayrade, 2006, ReCoSoC.

GECOS : Mécanisme de synchronisation passant à l’échelle à plusieurs lecteurs et un écrivain pour structures chaînées

Quentin L. Meunier, Alain Greiner, Franck Wajsbürt, 2015 .

STEPS: experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores

Alain Greiner, Mounir Benabdenbi, François Pêcheux, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

A language to desing generators of analog functions (poster)

Alain Greiner, Marie-Minerve Louërat, Vincent Bourguet, 2004, FDL.

Multilevel logic optimization of very high complexity circuits

Alain Greiner, Luc Burgun, N. Dictus, 1994, EURO-DAC '94.

A Low CostNetwork-on-Chip withGuaranteed ServiceWell Suited totheGALSApproach

Alain Greiner, 2006 .

Analog design for reuse - case study: very low-voltage sigma-delta modulator

Alain Greiner, Mohamed Dessouky, Andreas Kaiser, 2001, DATE '01.

Hierarchical Static Timing Analysis at Bull with HiTas

Alain Greiner, Karim Dioury, Marie-Minerve Rosset-Louërat, 2000 .

GENVIEW: a portable source-level debugger for macrocell generators

Alain Greiner, Frédéric Pétrot, François Pêcheux, 1991, Proceedings of the European Conference on Design Automation..

Managing the Shape Function of Analog Devices in a Slicing Tree Floorplan

Alain Greiner, Marie-Minerve Rosset-Louërat, Pierre Nguyen-Tuong, 2004 .

Use of MutiPhase Stability Intervals to handle Crosstalk with the Timing Analyzer hiTas

Alain Greiner, Karim Dioury, Marie-Minerve Louerat, 2002 .

Cycle precise core based hardware/software system simulation with predictable event propagation

Alain Greiner, Frédéric Pétrot, Denis Hommais, 1997, EUROMICRO 97. Proceedings of the 23rd EUROMICRO Conference: New Frontiers of Information Technology (Cat. No.97TB100167).

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

Alain Greiner, Ivan Miro Panades, Abbas Sheibanyrad, 2008, IEEE Design & Test of Computers.

Circuit Disassembly for Verification and functional Abstraction of CMOS Circuits

Alain Greiner, Pirouz Bazargan Sabet, Anthony Lester, 1998 .

SIMIPS : a cycle-precise interactive simulator for teaching microprocessor architecture

Alain Greiner, François Dromard, Yves Body, 1998 .

Decoupling Translation Lookaside Buffer Coherence from Cache Coherence

Quentin L. Meunier, Alain Greiner, Hao Liu, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Carrier Thermal Conductivity: Analysis and Application to Submicron-Device Simulation

Alain Greiner, Luca Reggiani, Maria Cristina Vecchi, 1998, VLSI Design.

Multilevel logic synthesis of very high complexity circuits

Alain Greiner, Luc Burgun, N. Dictus, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures

Alain Greiner, Ivan Miro Panades, A. Greiner, 2007, First International Symposium on Networks-on-Chip (NOCS'07).

NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCs

Alain Greiner, Christian Schwarz, Joel Porquet, 2011, 2011 Design, Automation & Test in Europe.

Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture

Fabien Clermidy, Alain Greiner, Ivan Miro-Panades, 2008 .

A redefinable symbolic simulation technique to testability design rules checking

Alain Greiner, Mokhtar Hirech, El Housseine Rejouan, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

STESOC: A Software-Based Test-Access-Mechanism Controller

Alain Greiner, Mounir Benabdenbi, Matthieu Tuna, 2006 .

A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

Alain Greiner, Zhen Zhang, Sami Taktak, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures

Alain Greiner, Abbas Sheibanyrad, 2006, PATMOS.

On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures

Alain Greiner, Frédéric Pétrot, Pascal Gomez, 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication Applications

Alain Greiner, Etienne Faure, Daniela Genius, 2006, ReCoSoC.

Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components

Alain Greiner, Mounir Benabdenbi, Zhen Zhang, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

A Portable Clock Multiplier Generator using Digital CMOS Standard Cells

Alain Greiner, Karim Dioury, Michel Combes, 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

Protocol and performance analysis of the MPC parallel computer

Alain Greiner, Olivier Glück, Amal Zerrouki, 2001, Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001.

RAPID-2, an object-oriented associative memory applicable to genome data processing

Alain Greiner, Pascal Faudemay, Denis Archambaud, 1994, 1994 Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences.

SPIN: a scalable, packet switched, on-chip micro-network

Alain Greiner, Cesar Albenes Zeferino, Laurent Mortiez, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Hierarchical Static Timing Analysis for CMOS ULSI Circuits

Alain Greiner, Karim Dioury, Marie-Minerve Rosset-Louërat, 1999 .

STESI: Testing wrapped IP cores using a dedicated Test Processor

Alain Greiner, Mounir Benabdenbi, Matthieu Tuna, 2005 .

Design Space Explorer : Un Outil de Co-Conception pour Plate-formes Multi-processeurs sur Puce

Alain Greiner, Daniela Genius, Nicolas Pouillon, 2008 .

Fast Functional SystemC Simulator using Static Scheduling

Alain Greiner, Richard Buchmann, 2005 .

A generic architecture for on-chip packet-switched interconnections

Alain Greiner, Pierre Guerrier, 2000, DATE '00.

ALLIANCE: A complete Set of CAD Tools for teaching VLSI Design

Alain Greiner, 1992 .

Adaptive Stackable 3D Cache Architecture for Manycores

Alain Greiner, Ivan Miro Panades, Eric Guthmuller, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Cache coherency and memory consistency in NoC based shared memory multiprocessor SoC architectures

Alain Greiner, Frédéric Pétrot, .