Cho W. Moon

An efficient heuristic procedure for solving the state assignment problem for event-based specifications

Robert K. Brayton, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Elimination of Dynamic Hazards by Factoring

Robert K. Brayton, Cho W. Moon, 1993, 30th ACM/IEEE Design Automation Conference.

Specification, synthesis, and verification of hazard-free asynchronous circuits

Robert K. Brayton, Paul R. Stephan, Cho W. Moon, 1994, J. VLSI Signal Process..

Solving the state assignment problem for signal transition graphs

Robert K. Brayton, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

A Delay Metric for RC Circuits Based on the Weibull Distribution

Luciano Lavagno, Malgorzata Marek-Sadowska, Rajeev Murgai, 2004 .

Sequential circuit design using synthesis and optimization

Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kanwar Jit Singh, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Performance-oriented technology mapping

Robert K. Brayton, Cho W. Moon, Albert Wang, 1990 .

Synthesis of hazard-free asynchronous circuits from graphical specifications

Robert K. Brayton, Paul R. Stephan, Cho W. Moon, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Timing model extraction of hierarchical blocks by graph reduction

Harish Kriplani, Krishna P. Belkhale, Cho W. Moon, 2002, DAC '02.