Taher Daud

发表

A VLSI neuroprocessor for dynamic assignment of resources

Silvio P. Eberhardt, Taher Daud, A. Thakoor, 1990, 1990 IEEE International Conference on Systems, Man, and Cybernetics Conference Proceedings.

Rapid evolution of analog circuits configured on a field programmable transistor array

Vu Duong, Adrian Stoica, Taher Daud, 2002 .

Predictability in space launch vehicle anomaly detection using intelligent neuro-fuzzy systems

Taher Daud, A. Thakoor, Sandeep Gulati, 1994 .

Self-Reconfigurable Analog Array Integrated Circuit Architecture for Space Applications

Adrian Stoica, Srinivas Katkoori, Taher Daud, 2008, 2008 NASA/ESA Conference on Adaptive Hardware and Systems.

Reconfigurable VLSI architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chips

Adrian Stoica, Taher Daud, Raoul Tawel, 2001, IEEE Trans. Very Large Scale Integr. Syst..

High-resolution synaptic weights and hardware-in-the-loop learning

Anilkumar P. Thakoor, Taher Daud, Tuan A. Duong, 1995, Electronic Imaging.

Transistor-Level Circuit Experiments Using Evolvable Hardware

Adrian Stoica, Taher Daud, Didier Keymeulen, 2005, IWINAC.

Evolution of analog circuits on field programmable transistor arrays

Vu Duong, Adrian Stoica, Taher Daud, 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

VIGILANTE: an advanced sensing/processing testbed for ATR applications

Anilkumar P. Thakoor, Wai-Chi Fang, Taher Daud, 1997, Defense, Security, and Sensing.

Cascade error projection: a new learning algorithm

A. R. Stubberud, Taher Daud, A. Thakoor, 1996, Proceedings of International Conference on Neural Networks (ICNN'96).

HONORS: : Advanced miniature processing hardware for ATR applications

Tien-Hsin Chao, Taher Daud, A. P. Thakoor, 1999, Neurocomputing.

Cascade Error Projection: A Learning Algorithm for Hardware Implementation

Taher Daud, Tuan A. Duong, T. Daud, 1999, IWANN.

The hardware results of a 64/spl times/64 analog input array for a 3-dimensional neural network processor

T. Duong, Anilkumar P. Thakoor, Taher Daud, 1998, 1998 IEEE International Joint Conference on Neural Networks Proceedings. IEEE World Congress on Computational Intelligence (Cat. No.98CH36227).

Feedforward, High Density, Programmable Read Only Neural Network Based Memory System

Taher Daud, Anil Thakoor, James L. Lamb, 1988, Photonics West - Lasers and Applications in Science and Engineering.

Analog parallel processor hardware for high-speed pattern recognition

Anilkumar P. Thakoor, Taher Daud, Raoul Tawel, 1990, Other Conferences.

Current mode circuits: increasing the chances of evolution to find a way

Vu Duong, Adrian Stoica, Taher Daud, 2002, Proceedings, IEEE Aerospace Conference.

Convergence Analysis of a Cascade Architecture Neural Network

Taher Daud, A. Thakoor, Tuan A. Duong, 1997 .

Analog VLSI neural networks: implementation issues and examples in optimization and supervised learning

Timothy X. Brown, Silvio P. Eberhardt, Taher Daud, 1992, IEEE Trans. Ind. Electron..

Adaptive and Evolvable Analog Electronics for Space Applications

Adrian Stoica, Srinivas Katkoori, Taher Daud, 2007, ICES.

Preliminary low temperature tests of a digital signal processor

Adrian Stoica, Taher Daud, Lukas Sekanina, 2005 .

Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications

Adrian Stoica, Taher Daud, Didier Keymeulen, 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

Programmable Analog Memory Resistors For Electronic Neural Networks

Anilkumar P. Thakoor, Taher Daud, Rajeshuni Ramesham, 1990 .

Speed challenge: a case for hardware implementation in soft-computing

R. Zebulum, T. Duong, Taher Daud, 2000 .

Non-Volatile Memory Technology Symposium 2001: Proceedings

Taher Daud, Nazeeh Aranki, Karl Strauss, 2001 .

Learning and optimization with cascaded VLSI neural network building-block chips

T. Duong, Taher Daud, Silvio P. Eberhardt, 1992, [Proceedings 1992] IJCNN International Joint Conference on Neural Networks.

Competitive neural architecture for hardware solution to the assignment problem

Timothy X. Brown, Taher Daud, A. P. Thakoor, 1991, Neural Networks.

Cascaded VLSI neural network chips: Hardware learning for pattern recognition and classification

Timothy X. Brown, Taher Daud, A. P. Thakoor, 1992, Simul..

Speed Enhancement with Soft Computing Hardware

Adrian Stoica, Taher Daud, Ian Ferguson, 2003, ICANN.

Cascade error projection with low bit weight quantization for high order correlation data

Taher Daud, Tuan A. Duong, 1999, IJCNN'99. International Joint Conference on Neural Networks. Proceedings (Cat. No.99CH36339).

Learning to Classify Map Data with Cascaded VLSI Neural Network Building Block Chips

Timothy X. Brown, T. Duong, Silvio P. Eberhardt, 1993 .

ELIPS: toward a sensor fusion processor on a chip

Taher Daud, Adrian Stoica, James A. Fabunmi, 1999, Defense, Security, and Sensing.

Analog 3-D Neuroprocessor for Fast Frame Focal Plane Image Processing

Taher Daud, Chris Saunders, Tuan A. Duong, 1995, Simul..

Radiation behavior of analog neural network chips

Taher Daud, A. Thakoor, F. Zee, 1996, Proceedings of International Conference on Neural Networks (ICNN'96).

Extended Logic Intelligent Processing System for a Sensor Fusion Processor Hardware

Taher Daud, Adrian Stoica, Wei-Te Li, 2000 .

A neural architecture for the assignment problem: simulation and VLSI implementation

Taher Daud, A. Thakoor, Silvio P. Eberhardt, 1991, IJCNN-91-Seattle International Joint Conference on Neural Networks.

Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core

Adrian Stoica, Srinivas Katkoori, Taher Daud, 2008, ICES.

High-speed VMEbus-based analog neurocomputing architecture for image classification

Anilkumar P. Thakoor, Taher Daud, Raoul Tawel, 1995, SPIE Defense + Commercial Sensing.

High-speed low-power analog ASICs for a 3D neuroprocessor

Anilkumar P. Thakoor, Taher Daud, Tuan A. Duong, 1995, Electronic Imaging.

Learning in neural networks: VLSI implementation strategies

Taher Daud, A. Thakoor, Tuan A. Duong, 1996 .

Low power analog neurosynapse chips for a 3-D "sugarcube" neuroprocessor

John S. Carson, T. Duong, Taher Daud, 1994, Proceedings of 1994 IEEE International Conference on Neural Networks (ICNN'94).

Evolvable Hardware for Extreme Environments: Hot or Cold

R. Zebulum, Taher Daud, A. Thakoor, 2001 .

Europa Orbiter: Mass Memory Requirements and Status

Taher Daud, Alan Nicholson, Dan Karmon, 2001 .

Cascaded VLSI Chips Help Neural Network To Learn

Anilkumar P. Thakoor, Taher Daud, Tuan A. Duong, 1993 .

Evolutionary recovery of electronic circuits from radiation induced faults

Vu Duong, Adrian Stoica, Tughrul Arslan, 2004, Proceedings of the 2004 Congress on Evolutionary Computation (IEEE Cat. No.04TH8753).

Winner/loser-take-all circuits on SOI technology for neural network classification

Taher Daud, Chris Saunders, Tuan A. Duong, 1998, Defense, Security, and Sensing.

Solid-state reprogrammable analog resistive devices for electronic neural networks

Taher Daud, Rajeshuni Ramesham, A. P. Thakoor, 1990 .

Charge-Coupled Device Advances For X-Ray Scientific Applications In 1986

Taher Daud, James R. Janesick, Tom Elliott, 1987 .

Charge-coupled-device response to electron beam energies of less than 1 keV up to 20 keV

Taher Daud, James R. Janesick, Tom Elliott, 1987 .

Front surface passivation of silicon solar cells with antireflection coating

Taher Daud, G. T. Crotty, G. Crotty, 1987 .

Flash Technology For Charge-Coupled-Device Imaging In The Ultraviolet

Taher Daud, James R. Janesick, Tom Elliott, 1987 .

Solid‐state thin‐film memistor for electronic neural networks

Taher Daud, A. P. Thakoor, A. Moopenn, 1990 .