M.H. Park

PI controller gains tuning of the pressure control system by open-loop frequency response (thermal power plants)

H.S. Mok, G.T. Kim, M.H. Park, 1988, Conference Record of the 1988 IEEE Industry Applications Society Annual Meeting.

Operational PRAM analysis with PVT variations using process-aware compact model

Y.T. Kim, Y.K. Park, K.J. Lee, 2008, 2008 International Conference on Simulation of Semiconductor Processes and Devices.

Design-friendly scalability of cost-effective 28LP technology platform featuring 2nd generation gate-first HK/MG transistors without eSiGe

Y.S. Kim, S.C. Kim, M.H. Park, 2011, 2011 International Electron Devices Meeting.

50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications

M.H. Park, H.S. Kang, D.H. Lee, 2002, Digest. International Electron Devices Meeting,.

Stress minimization in deep sub-micron full CMOS devices by using an optimized combination of the trench filling CVD oxides

S.H. Hong, M.Y. Lee, M.H. Park, 1997, International Electron Devices Meeting. IEDM Technical Digest.

A novel simple shallow trench isolation (SSTI) technology using high selective CeO/sub 2/ slurry and liner SiN as a CMP stopper

M.Y. Lee, M.H. Park, H.K. Kang, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).