T. Higashi

Memory design using one-transistor gain cell on SOI

T. Ohsawa, K. Fujita, T. Higashi, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

Design of a 128-mb SOI DRAM using the floating body cell (FBC)

T. Ohsawa, T. Higashi, T. Furuyama, 2006, IEEE Journal of Solid-State Circuits.

Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

T. Ohsawa, T. Higashi, A. Nitayama, 2006, 2006 International Electron Devices Meeting.

Array architecture of floating body cell (FBC) with quasi-shielded open bit line scheme for sub-40nm node

T. Ohsawa, T. Higashi, F. Matsuoka, 2008, 2008 IEEE International SOI Conference.

Flip-flop selection technique for power-delay trade-off [video codec]

T. Higashi, M. Hamada, Y. Watanabe, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

350 MHz time-multiplexed 8-port SRAM and word size variable multiplier for multimedia DSP

T. Sakurai, T. Higashi, F. Hatori, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.