T. Miyaba

A channel-erasing 1.8 V-only 32 Mb NOR flash EEPROM with a bit-line direct-sensing scheme

T. Watanabe, Y. Takano, S. Atsumi, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

A sampling weak-program method to tighten Vth-distribution of 0.5 V for low-voltage flash memories

S. Atsumi, M. Saito, H. Shiga, 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme

H. Watanabe, S. Yamada, Y. Takano, 2000, IEEE Journal of Solid-State Circuits.

A 44 mm/sup 2/ 4-bank 8-word page read 64 Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

H. Watanabe, Y. Takano, S. Atsumi, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A 3.3 V-only 16 Mb flash memory with row-decoding scheme

Y. Iyama, A. Umezawa, S. Atsumi, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.