J. De Vos

First Demonstration of Hybrid CMOS Imagers With Simultaneous Very Low Crosstalk and High-Broadband Quantum Efficiency

C. Van Hoof, P. De Moor, K. Minoglou, 2012, IEEE Transactions on Electron Devices.

A new scalable self-aligned dual-bit split-gate charge-trapping memory device

J. De Vos, L. Haspeslagh, L. Breuil, 2005, IEEE Transactions on Electron Devices.

In-line metrology for characterization and control of extreme wafer thinning of bonded wafers

E. Beyne, J. De Vos, A. Jourdain, 2017, 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO).

Process development to enable die sorting and 3D IC stacking

E. Beyne, J. De Vos, A. La Manna, 2012, 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).

Process related challenges for 3D face to face stacking test vehicles using a 40/50μm pitch CuSn microbump configuration

J. De Vos, C. Gerets, A. La Manna, 2012, 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).

Key elements for sub-50μm pitch micro bump processes

E. Beyne, J. De Vos, C. Gerets, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

A scalable Stacked Gate NOR/NAND Flash Technology compatible with high-k and metal gates for sub 45nm generations

J. De Vos, L. Haspeslagh, D. Wellekens, 2006, 2006 IEEE International Conference on IC Design and Technology.

Optimization of Al2O3 Interpoly Dielectric for Embedded Flash Memory Applications

J. De Vos, D. Wellekens, J. Van Houdt, 2008, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design.

Investigation of the low-field leakage through high-k interpoly dielectric stacks and its impact on nonvolatile memory data retention

J. De Vos, L. Haspeslagh, B. Govoreanu, 2006, 2006 International Electron Devices Meeting.

Scalable Floating Gate Flash Memory CellWith Engineered Tunnel Dielectric and High-K (Al2O3) Interpoly Dielectric

J. De Vos, P. Blomme, J.V. Houdt, 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.

Investigation of TSV noise coupling in 3D-ICs using an experimental validated 3D TSV circuit model including Si substrate effects and TSV capacitance inversion behavior after wafer thinning

E. Beyne, J. De Vos, G. Van der Plas, 2016, 2016 IEEE MTT-S International Microwave Symposium (IMS).

High density 20μm pitch CuSn microbump process for high-end 3D applications

P. Soussan, K. De Munck, J. De Vos, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).