Amir Masoud Gharehbaghi

发表

Specification and formal verification of power gating in processors

Masahiro Fujita, Amir Masoud Gharehbaghi, 2014, Fifteenth International Symposium on Quality Electronic Design.

Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults

Masahiro Fujita, Amir Masoud Gharehbaghi, Peikun Wang, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Automatic Test Pattern Generation for Multiple Stuck-At Faults: When Testing for Single Faults is Insufficient

Amir Masoud Gharehbaghi, Fujita Masahiro, Conrad Jinyong Moore, 2016 .

An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults

Masahiro Fujita, Amir Masoud Gharehbaghi, Peikun Wang, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Signal Selection Methods for Debugging Gate-Level Sequential Circuits

Masahiro Fujita, Amir Masoud Gharehbaghi, Yusuke Kimura, 2019, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Transaction-based post-silicon debug of many-core System-on-Chips

Masahiro Fujita, Amir Masoud Gharehbaghi, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns

Amir Masoud Gharehbaghi, Masahiro Fujita, Peikun Wang, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Debugging from high level down to gate level

Masahiro Fujita, Amir Masoud Gharehbaghi, Yoshihisa Kojima, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Behavioral test generation for VHDL processes

Amir Masoud Gharehbaghi, Zain Navabi, 2000, ICM 2000. Proceedings of the 12th International Conference on Microelectronics. (IEEE Cat. No.00EX453).

Debugging processors with advanced features by reprogramming LUTs on FPGA

Masahiro Fujita, Takeshi Matsumoto, Amir Masoud Gharehbaghi, 2013, 2013 International Conference on Field-Programmable Technology (FPT).

High-Level Engineering Change Through Programmable Datapath and SMT Solvers

Amir Masoud Gharehbaghi, Masahiro Fujita, Qinhao Wang, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model

Masahiro Fujita, Amir Masoud Gharehbaghi, M. Fujita, 2014, IEICE Trans. Inf. Syst..

Rectification of advanced microprocessors without changing routing on FPGAs (abstract only)

Masahiro Fujita, Takeshi Matsumoto, Amir Masoud Gharehbaghi, 2013, FPGA '13.

A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality

Masahiro Fujita, Amir Masoud Gharehbaghi, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Fast and Efficient Signature-Based Sub-Circuit Matching

Masahiro Fujita, Amir Masoud Gharehbaghi, M. Fujita, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations

Yukio Miyasaka, Amir Masoud Gharehbaghi, Masahiro Fujita, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Timing verification of distributed network systems at higher levels of abstraction

Shaahin Hessabi, Amir Masoud Gharehbaghi, Hassan Hatefi-Ardakani, 2008, 2008 IEEE International High Level Design Validation and Test Workshop.

Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only)

Masahiro Fujita, Amir Masoud Gharehbaghi, Bijan Alizadeh, 2010, FPGA '10.

SRAM-Based Synthesis for Multi-Output Gates

Amir Masoud Gharehbaghi, Fujita Masahiro, Le Xingming, 2019 .

A new approach for diagnosing bridging faults in logic designs

Masahiro Fujita, Amir Masoud Gharehbaghi, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Efficient Graph Matching Method for LUT-Networks (リコンフィギャラブルシステム)

Masahiro Fujita, Amir Masoud Gharehbaghi, Hossein Izadi Rad, 2016 .

Formal verification guided automatic design error diagnosis and correction of complex processors

Masahiro Fujita, Amir Masoud Gharehbaghi, 2011, 2011 IEEE International High Level Design Validation and Test Workshop.

Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints

Yukio Miyasaka, Amir Masoud Gharehbaghi, Masahiro Fujita, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

C Description Reconstruction Method from a Revised Netlist for ECO Support

Masahiro Fujita, Amir Masoud Gharehbaghi, Yusuke Kimura, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Efficient Graph Matching Method for LUT-Networks (VLSI設計技術)

Masahiro Fujita, Amir Masoud Gharehbaghi, Hossein Izadi Rad, 2016 .

Trace signal selection methods for post silicon debugging

Masahiro Fujita, Takeshi Matsumoto, Amir Masoud Gharehbaghi, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

A new approach for constructing logic functions after ECO

Masahiro Fujita, Amir Masoud Gharehbaghi, 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Pipelined Microprocessors Optimization and Debugging

Masahiro Fujita, Amir Masoud Gharehbaghi, Bijan Alizadeh, 2010, ARC.

Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme

Masahiro Fujita, Shinji Kimura, Amir Masoud Gharehbaghi, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

Template-based C Description Generation after ECO at RTL Design Stage

Amir Masoud Gharehbaghi, Kimura Yusuke, Fujita Masahiro, 2017 .

Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints

Masahiro Fujita, Yukio Miyasaka, Amir Masoud Gharehbaghi, 2020, 2020 21st International Symposium on Quality Electronic Design (ISQED).

System-Level Assertion-Based Performance Verification for Embedded Systems

Shaahin Hessabi, Amir Masoud Gharehbaghi, Hassan Hatefi-Ardakani, 2008 .

Transaction Ordering in Network-on-Chips for Post-Silicon Validation

Masahiro Fujita, Amir Masoud Gharehbaghi, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A new approach for selecting inputs of logic functions during debug

Masahiro Fujita, Amir Masoud Gharehbaghi, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

Efficient signature-based sub-circuit matching

Masahiro Fujita, Amir Masoud Gharehbaghi, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

A New Reconfigurable Architecture with Applications to IoT and Mobile Computing

Masahiro Fujita, Amir Masoud Gharehbaghi, Tomohiro Maruoka, 2018, IFIPIoT@WCC.

An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults

Masahiro Fujita, Amir Masoud Gharehbaghi, Peikun Wang, 2019, 2019 IEEE 37th VLSI Test Symposium (VTS).

On-chip transaction level debug support for system-on-chips

Masahiro Fujita, Amir Masoud Gharehbaghi, 2009, 2009 International SoC Design Conference (ISOCC).

Post Silicon Debugging of Electrical Bugs Using Trace Buffers

Mehdi Baradaran Tahoori, Masahiro Fujita, Amir Masoud Gharehbaghi, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

A low-cost approximate 32-point transform architecture

Masahiro Fujita, Shinji Kimura, Amir Masoud Gharehbaghi, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Approximate Arithmetic Circuit Design Using a Fast and Scalable Method

Masahiro Fujita, Amir Masoud Gharehbaghi, Qi Lu, 2019, 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC).

Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults

Masahiro Fujita, Amir Masoud Gharehbaghi, Peikun Wang, 2019, 20th International Symposium on Quality Electronic Design (ISQED).

Transaction-based debugging of system-on-chips with patterns

Masahiro Fujita, Amir Masoud Gharehbaghi, 2009, 2009 IEEE International Conference on Computer Design.

AIRE/CE: a revision towards CAD tool integration

Zainalabedin Navabi, Amir Masoud Gharehbaghi, M. H. Reshadi, 2000, ICM 2000. Proceedings of the 12th International Conference on Microelectronics. (IEEE Cat. No.00EX453).

Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods

Masahiro Fujita, Amir Masoud Gharehbaghi, M. Fujita, 2012, 2012 IEEE 21st Asian Test Symposium.

Global transaction ordering in Network-on-Chips for post-silicon validation

Masahiro Fujita, Amir Masoud Gharehbaghi, 2011, 2011 12th International Symposium on Quality Electronic Design.

Automatic rectification of design errors in complex processors with programmable hardware

Masahiro Fujita, Amir Masoud Gharehbaghi, 2012, 2012 International Conference on Field-Programmable Technology.

An assertion-based verification methodology for system-level design

Shaahin Hessabi, Maziar Goudarzi, Amir Masoud Gharehbaghi, 2007, Comput. Electr. Eng..

Signal Selection Methods for Efficient Multi-Target Correction

Masahiro Fujita, Amir Masoud Gharehbaghi, Yusuke Kimura, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Formal Verification and Debugging of VLSI Logic Design for Systems Dependability: Experiments and Evaluation

Kazutoshi Wakabayashi, Takashi Takenaka, Hiroaki Yoshida, 2019 .

Intermediate Format Standardization : Ambiguities , Deficiencies , Portability issues , Documentation and Improvements

Zainalabedin Navabi, Amir Masoud Gharehbaghi, Mohammad Hossein Reshadi, 2003 .