Guillaume Duc

Optimizing System Architecture Cost and Security Countermeasures

Ludovic Apvrille, Guillaume Duc, Sahar Berro, 2019, GraMSec@CSF.

Hardware-assisted Memory Tracing on New SoCs Embedding FPGA Fabrics

Renaud Pacalet, Guillaume Duc, Letitia W. Li, 2015, ACSAC.

Java Card Operand Stack: Fault Attacks, Combined Attacks and Countermeasures

Guillaume Barbu, Guillaume Duc, Philippe Hoogvorst, 2011, CARDIS.

BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation

Sylvain Guilley, Jean-Luc Danger, Maxime Nassar, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest

K. Ohta, J. Danger, Nicolas Veyrat-Charvillon, 2014, Journal of Cryptographic Engineering.

Education and open benchmarking on side-channel analysis with the DPA contests

Sylvain Guilley, Jean-Luc Danger, Guillaume Duc, 2011 .

Application-Replay Attack on Java Cards: When the Garbage Collector Gets Confused

Guillaume Barbu, Guillaume Duc, Philippe Hoogvorst, 2012, ESSoS.