Lih-Yih Chiou

发表

Simultaneous partitioning, scheduling and allocation for synthesis of multi-chip module architectures

M. A. Bayoumi, R. V. Cherabuddi, Lih-Yih Chiou, 1994, Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing.

Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F2/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM

Heng-Yuan Lee, Lih-Yih Chiou, Tsai-Kan Chien, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

Circuit design challenges and trends in read sensing schemes for resistive-type emerging nonvolatile memory

Meng-Fan Chang, Heng-Yuan Lee, Frederick T. Chen, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

A low store energy and robust ReRAM-based flip-flop for normally off microprocessors

Ming-Jinn Tsai, Lih-Yih Chiou, Pei-Hua Wang, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Methodology for developing virtual platforms from power-aware to power- and thermal-aware at electronic system level

Lih-Yih Chiou, Liang-Ying Lu, Tsung-Yu Hsieh, 2018, IET Cyper-Phys. Syst.: Theory & Appl..

DSP data path synthesis for low-power applications

Khurram Muhammad, Kaushik Roy, Lih-Yih Chiou, 2001, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221).

Intelligent Policy Selection for GPU Warp Scheduler

Lih-Yih Chiou, Yeong-Jar Chang, Tsung-Han Yang, 2019, 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS).

Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering

Kaushik Roy, Hunsoo Choo, Hamid Mahmoodi, 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

Design of A 0.3V–1.2V wide input range solar energy harvesting circuit with high converting power efficiency

Lih-Yih Chiou, Sheng-Kai Lo, Wei-Jhe Lin, 2016, 2016 2nd International Conference on Intelligent Green Building and Smart Grid (IGBSG).

A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits

Ming-Hung Wu, Lih-Yih Chiou, Chi-Ray Huang, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches

Ming-Jinn Tsai, Lih-Yih Chiou, Pei-Hua Wang, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs

Lih-Yih Chiou, Jing-Yu Huang, Chi-Ray Huang, 2019, 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A limited-contention cross-coupled level shifter for energy-efficient subthreshold-to-superthreshold voltage conversion

Lih-Yih Chiou, Chi-Ray Huang, L. Chiou, 2014, 2014 International SoC Design Conference (ISOCC).

An ultra-low-power adaptive-body-bias control for subthreshold circuits

Lih-Yih Chiou, Shien-Chun Luo, Chi-Ray Huang, 2014, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

The SoC design of a versatile biomedical signal processor for potentiostat

Chung-Ho Chen, Bin-Da Liu, Soon-Jyh Chang, 2015, 2015 International Symposium on Bioelectronics and Bioinformatics (ISBB).

An energy-efficient nonvolatile microprocessor considering software-hardware interaction for energy harvesting applications

Lih-Yih Chiou, Ming-Jinn Tsai, Tsai-Kan Chien, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Aggressive look-ahead earliest deadline first algorithm

Lih-Yih Chiou, Hsin-Ei Lim, Yi-Siou Chen, 2007, TENCON 2007 - 2007 IEEE Region 10 Conference.

Buffer size minimization method considering mix-clock domains and discontinuous data access

Lih-Yih Chiou, Alan P. Su, Liang-Ying Lu, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Temperature Gradient Exploration Method for Determining the Appropriate Number of Cells in Mesh-Based Thermal Analysis

Lih-Yih Chiou, Liang-Ying Lu, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A subthreshold SRAM cell with autonomous bitline-voltage clamping

Lih-Yih Chiou, Shien-Chun Luo, 2010, 2010 International Symposium on Next Generation Electronics.

A fast and effective dynamic trace-based method for analyzing architectural performance

Lih-Yih Chiou, Yi-Siou Chen, Hsun-Hsiang Chang, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing

Lih-Yih Chiou, Shien-Chun Luo, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

Synthesis of application-specific highly-efficient multi-mode systems for low-power applications

Kaushik Roy, Swarup Bhunia, Lih-Yih Chiou, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications

Kaushik Roy, Khurram Muhammad, Lih-Yih Chiou, 2001, VLSI Design.

An effective matrix compression method for GPU-accelerated thermal analysis

Lih-Yih Chiou, Liang-Ying Lu, Chieh-Yu Lin, 2015, VLSI Design, Automation and Test(VLSI-DAT).

Synthesis of application-specific highly efficient multi-mode cores for embedded systems

Kaushik Roy, Swarup Bhunia, Lih-Yih Chiou, 2005, TECS.

Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications

Ming-Jinn Tsai, Lih-Yih Chiou, Tsai-Kan Chien, 2016, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

A Reliable Delay-Based Physical Unclonable Function with Dark-Bit Avoidance

Lih-Yih Chiou, Chung-Han Wu, Po-Cheng Wei, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Efficient Four-Coil Wireless Power Transfer for Deep Brain Stimulation

Soon-Jyh Chang, Lih-Yih Chiou, Chin-Lung Yang, 2017, IEEE Transactions on Microwave Theory and Techniques.

System thermal analysis of 3D IC on ESL virtual platform

Jen-Chieh Yeh, Lih-Yih Chiou, Liang-Ying Lu, 2013, 2013 International SoC Design Conference (ISOCC).

Temperature gradient-aware thermal simulator for three-dimensional integrated circuits

Lih-Yih Chiou, Liang-Ying Lu, L. Chiou, 2017, IET Comput. Digit. Tech..

Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion

Lih-Yih Chiou, Shien-Chun Luo, Chi-Ray Huang, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering

Kaushik Roy, Hunsoo Choo, Hamid Mahmoodi, 2010, J. Signal Process. Syst..

Crosstalk-insensitive via-programming ROMs using content-aware design framework

Meng-Fan Chang, Kuei-Ann Wen, Lih-Yih Chiou, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme

Lih-Yih Chiou, Chung-Han Wu, Chi-Ray Huang, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation

Lih-Yih Chiou, Chi-Ray Huang, L. Chiou, 2018, IET Circuits Devices Syst..

An Efficient VLSI Architecture of Frequency Domain Kurtosis for Non-Stationary Acoustic Noise Measurements

Lih-Yih Chiou, Sheau-Fang Lei, Hsieh-Wei Lee, 2006, 2006 International Conference on Communications, Circuits and Systems.

A Data-Traffic Aware Dynamic Power Management for General-Purpose Graphics Processing Units

Lih-Yih Chiou, Chao-Kai Yang, Che-Pin Chang, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop

Soon-Jyh Chang, Lih-Yih Chiou, Yen-Ting Liu, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics

Lih-Yih Chiou, Shien-Chun Luo, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop

Lih-Yih Chiou, Shien-Chun Luo, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Active Filter Based On-Chip Step-Down DC-DC Switching Voltage Regulator

Le-Ren Chang-Chien, Lih-Yih Chiou, Chun-Hsun Wu, 2005, TENCON 2005 - 2005 IEEE Region 10 Conference.

A low supply noise content-sensitive ROM architecture for SOC

Meng-Fan Chang, Kuei-Ann Wen, Lih-Yih Chiou, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

Energy-aware partitioning for on-chip bus architecture using a multi-objective genetic algorithm

Lih-Yih Chiou, Yi-Siou Chen, Ya-Lun Jian, 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling

Chung-Ho Chen, Kuen-Jong Lee, Jai-Ming Lin, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

A VLSI architecture for modified frequency sensitive self-organizing neural network for image data compression

M. A. Bayoumi, Lih-Yih Chiou, J. Limqueco, 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

A 300mV Sub-1pJ differential 6T sub-threshold SRAM with low energy and variability resilient local assist circuit

Lih-Yih Chiou, Yu-Lin Tsai, Chi-Ray Huang, 2013, 2013 International Symposium on Next-Generation Electronics.

System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm

Lih-Yih Chiou, Chih-Hsien Lee, Yi-Siou Chen, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Peak current reduction using an MTCMOS technique

Lih-Yih Chiou, Liang-Ying Lu, Jing-Wen Shi, 2010, 2nd Asia Symposium on Quality Electronic Design (ASQED).

Adaptive minimum supply voltage for subthreshold circuits considering noise margin and PT variations

Lih-Yih Chiou, Shien-Chun Luo, 2010, The 2010 International Conference on Green Circuits and Systems.

Leakage control with efficient use of transistor stacks in single threshold CMOS

Mark C. Johnson, Kaushik Roy, Lih-Yih Chiou, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture

Ming-Jinn Tsai, Lih-Yih Chiou, Pei-Hua Wang, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A novel clock-pulse-width calibration technique for charge redistribution DACs

Lih-Yih Chiou, Hong-Yi Huang, Ching-Hsing Luo, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Leakage current reduction in CMOS logic circuits

Bin-Da Liu, Lih-Yih Chiou, Heng-Yao Lin, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

Fast Steady-State Thermal Analysis

Lih-Yih Chiou, Yeong-Jar Chang, Liang-Ying Lu, 2018, 2018 International SoC Design Conference (ISOCC).

An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM

Lih-Yih Chiou, Chi-Ray Huang, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Reliable Near-Threshold Voltage SRAM-Based PUF Utilizing Weight Detection Technique

Lih-Yih Chiou, Jing-Yu Huang, Chi-Kuan Li, 2021, 2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).