José Luis Neves

发表

Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew

Eby G. Friedman, José Luis Neves, E. Friedman, 1996, IEEE Trans. Very Large Scale Integr. Syst..

Repeater insertion in tree structured inductive interconnect

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Minimizing power dissipation in non-zero skew-based clock distribution networks

Eby G. Friedman, José Luis Neves, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Equivalent Elmore delay for RLC trees

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Optimal clock skew scheduling tolerant to process variations

Eby G. Friedman, José Luis Neves, 1996, DAC '96.

Automated Synthesis of Skew-Based Clock Distribution Networks

Eby G. Friedman, José Luis Neves, 1998, VLSI Design.

Power dissipated by CMOS gates driving lossless transmission lines

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

Figures of merit to characterize the importance of on-chip inductance

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Exploiting the on-chip inductance in high-speed clock distribution networks

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Steiner tree optimization for buffers. Blockages and bays

Sachin S. Sapatnekar, Jiang Hu, José Luis Neves, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Equivalent Elmore delay for RLC trees

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 1999, DAC '99.

Buffer library selection

José Luis Neves, Stephen T. Quay, J. Neves, 2000, Proceedings 2000 International Conference on Computer Design.

Steiner tree optimization for buffers, blockages, and bays

Sachin S. Sapatnekar, Jiang Hu, José Luis Neves, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Inductance Effects in RLC Trees

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 2002, J. Circuits Syst. Comput..

Signal waveform characterization in RLC trees

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Parallelizing post-placement timing optimization

Marios C. Papaefthymiou, José Luis Neves, Jiyoun Kim, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

Circuit synthesis of clock distribution networks based on non-zero clock skew

Eby G. Friedman, José Luis Neves, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

IBM z14 design methodology enhancements in the 14-nm technology node

José Luis Neves, Alper Buyuktosunoglu, Ofer Geva, 2018, IBM J. Res. Dev..

Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations

Eby G. Friedman, José Luis Neves, 1997, J. VLSI Signal Process..

Dynamic and short-circuit power of CMOS gates driving lossless transmission lines

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

Inductance effects in RLC trees

Yehea I. Ismail, Eby G. Friedman, José Luis Neves, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.