Larysa Titarenko

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Synthesis of basic circuits of compositional microprogram control units

Alexander Barkalov, Larysa Titarenko, 2008 .

Methods of Neural Networks in Control of Telecommunication Systems

Alexander Barkalov, Larysa Titarenko, Vladimir Popovskij, 2011 .

8 Synthesis of Compositional Microprogram Control Unit with Dedicated Area of Inputs

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2011 .

Design of EMB-Based Mealy FSMs

Alexander Barkalov, Larysa Titarenko, Grzegorz Bazydlo, 2016 .

Field Programmable Gate Arrays in FSM Design

Alexander Barkalov, Larysa Titarenko, Grzegorz Bazydlo, 2016 .

Twofold State Assignment for LUT-based Mealy FSMs

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2018, 2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES).

General Information about Controlled Systems

Alexander Barkalov, Larysa Titarenko, Vladimir Popovskij, 2011 .

Implementing Control Units for Linear Algorithms

Alexander Barkalov, Larysa Titarenko, Alexander Miroshkin, 2012 .

Synthesis and Optimization of FPGA-Based Systems

Alexander Barkalov, Larysa Titarenko, Valery Sklyarov, 2014 .

FPGA Architectures, Reconfigurable Fabric, Embedded Blocks and Design Tools

Alexander Barkalov, Larysa Titarenko, Valery Sklyarov, 2014 .

Embedded Blocks and System-Level Design

Alexander Barkalov, Larysa Titarenko, Valery Sklyarov, 2014 .

Programmable Logic Controllers

Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz, 2019 .

Logic Synthesis for FPGA-Based Finite State Machines

Alexander Barkalov, Larysa Titarenko, Grzegorz Bazydlo, 2015 .

Design of EMB-Based Moore FSMs

Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, 2017, J. Circuits Syst. Comput..

Design of CPLD-based mealy FSMs with counters

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, 2018, 2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST).

Improving Characteristics of LUT-Based Moore FSMs

Alexander Barkalov, Larysa Titarenko, Sławomir Chmielewski, 2020, IEEE Access.

Taught Controlled Systems

Alexander Barkalov, Larysa Titarenko, Vladimir Popovskij, 2011 .

OPTIMIZATION OF CONTROL UNIT WITH CODE SHARING

Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, 2006 .

Matrix Realization of Control Units

Alexander Barkalov, Larysa Titarenko, A. Barkalov, 2009 .

OPTIMIZATION OF CMCU WITH BASE STRUCTURE DEDICATED FOR CPLD SYSTEMS

Alexander Barkalov, Larysa Titarenko, Ëukasz Smoli, 2012 .

Synthesis of compositional control unit with modified operational linear chains

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2009, 2009 10th International Conference - The Experience of Designing and Application of CAD Systems in Microelectronics.

Control memory optimization for compositional microprogram control units with code sharing

Alexander Barkalov, Larysa Titarenko, 2008 .

Designing FPGA-Based Mealy FSMs with Two Levels of Logic

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2019, 2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST).

FSM Synthesis with Elementary Chains

Alexander Barkalov, Larysa Titarenko, 2009 .

Encoding of Terms in LUT-based Mealy FSMs

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2018, 2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES).

Hardware reduction for FSM - Based control units using PAL technology

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, 2010, 2010 East-West Design & Test Symposium (EWDTS).

Hardware Reduction for Lut–Based Mealy FSMs

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2018, Int. J. Appl. Math. Comput. Sci..

Organization of Control Units with Operational Addressing

Alexander Barkalov, Larysa Titarenko, Roman M. Babakov, 2012 .

FSM-Based Models of Control Units

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2020 .

Logic Synthesis for Finite State Machines Based on Linear Chains of States

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2018 .

Microprogram control unit with code sharing and extended microinstruction format

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2010, 2010 East-West Design & Test Symposium (EWDTS).

Synthesis of Moore finite state machine with nonstandard presentation of state codes

Alexander Barkalov, Larysa Titarenko, O. Hebda, 2010 .

Implementation of Computational Algorithms in Embedded Systems

Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz, 2019 .

Design of microprogrammed controllers to be implemented in FPGAs

Wolfgang A. Halang, Alexander Barkalov, Larysa Titarenko, 2011, Int. J. Appl. Math. Comput. Sci..

Introduction into Embedded Systems

Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz, 2019 .

Features of ASSP under Different Levels of A-Priori Uncertainty

Alexander Barkalov, Larysa Titarenko, 2013 .

Synthesis of PLA-Based Moore FSM with Unconventional Presentation of State Codes

Alexander Barkalov, Larysa Titarenko, Olena Hebda, 2013, PDeS.

Mixed Encoding of Microoperations

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2020 .

Design of FSMs with Embedded Memory Blocks

Alexander Barkalov, Larysa Titarenko, Valery Sklyarov, 2014 .

Analysis of Resource Utilization in Compositional Microprogram Control Unit with Elementary Operational Linear Chains

Larysa Titarenko, Malgorzata Kolopienczyk, 2009 .

Hardware Reduction in Logic Circuits of Moore FSM

Alexander Barkalov, Larysa Titarenko, Valery Sklyarov, 2014 .

Modification of Elementary Operational Linear Chains in Compositional Control Unit with Code Sharing

Larysa Titarenko, Aleksander Barkalov, Aleksander N. Miroshkin, 2009 .

EMB - Based Design of Mealy FSM

Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, 2013, PDeS.

State Machines Synthesis and Implementation into FPGAs with Multiple Encoding of States

Alexander Barkalov, Larysa Titarenko, Arkadiusz Bukowiec, 2008 .

Design of EMB-Based Moore FSMs

Alexander Barkalov, Larysa Titarenko, Grzegorz Bazydlo, 2017 .

Design of moore finite state machine with extended state codes

Alexander Barkalov, Larysa Titarenko, Olena Hebda, 2013, Proceedings of the ITI 2013 35th International Conference on Information Technology Interfaces.

Synthesis of control unit with refined state encoding for CPLD devices

Larysa Titarenko, S. Chmielewski, Aleksander Barkalov, 2011, 2011 9th East-West Design & Test Symposium (EWDTS).

SYNTHESIS OF SIGNALS ADAPTIVE SPATIAL PROCESSING ROBUST ALGORITHMS ON THE BASE OF THE PROBABILISTIC APPROACH

Larysa Titarenko, Alexandr Barkalov, 2005 .

Synthesis of Control Algorithms for Telecommunication Systems

Alexander Barkalov, Larysa Titarenko, Vladimir Popovskij, 2011 .

Synthesis of Mealy FSMs with Counters

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2020 .

Design of Embedded Systems

Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz, 2019 .

Linear Chains in FSMs

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2018 .

Reducing LUT Count for FPGA-Based Mealy FSMs

Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki, 2020 .

Hardwired Interpretation of Control Algorithms

Alexander Barkalov, Larysa Titarenko, 2009 .

Twofold state assignment for FPGA-based mealy FSMs

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2018, 2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST).

Encoding of Terms in EMB-Based Mealy FSMs

Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki, 2020, Applied Sciences.

Design of FPGA-based Mealy FSMs with Counters

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2018, 2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES).

General Characteristic of Methods for STSP

Alexander Barkalov, Larysa Titarenko, 2013 .

Encoding of Microoperations in FPGA-Based Moore FSMs

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2019, 2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST).

Synthesis of ASF Algorithms for Not Exactly Known Parameters

Alexander Barkalov, Larysa Titarenko, A. Barkalov, 2013 .

Minimization of the number of PAL macrocells for Moore FSM

Larysa Titarenko, Slawomir Chmielewski, Aleksander Barkalov, 2009, 2009 10th International Conference - The Experience of Designing and Application of CAD Systems in Microelectronics.

Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, 2007, Int. J. Appl. Math. Comput. Sci..

CloudBus protocol hardware multi-converter gateway for distributed embedded systems

Alexander Barkalov, Larysa Titarenko, Grzegorz Andrzejewski, 2017, 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems.

Design of FPGA-Based Moore FMSs with Counters

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2013, PDeS.

Logic Synthesis for FPGA-Based Control Units - Structural Decomposition in Logic Design

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2020, Lecture Notes in Electrical Engineering.

Synthesis of compositional microprogram control units with code sharing

Alexander Barkalov, Larysa Titarenko, 2008 .

Designing HFPGA-based Mealy FSMs with transformation of output functions

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2017, 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems.

Mathematical Models and Principles of Control in TCS

Alexander Barkalov, Larysa Titarenko, Vladimir Popovskij, 2011 .

Structural Decomposition in FSM Synthesis

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2020 .

Finite State Machines and Field-Programmable Gate Arrays

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2018 .

Logic Synthesis for Compositional Microprogram Control Units

Alexander Barkalov, Larysa Titarenko, 2008, Lecture Notes in Electrical Engineering.

Matrix implementation of Moore FSM with nonstandard presentation of state codes

Larysa Titarenko, Olena Hebda, 2013, East-West Design & Test Symposium (EWDTS 2013).

Recursive Estimates of States of Network Elements

Alexander Barkalov, Larysa Titarenko, Vladimir Popovskij, 2011 .

Methods of Signal Processing for Adaptive Antenna Arrays

Alexander Barkalov, Larysa Titarenko, 2012 .

Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs

Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki, 2020 .

Synthesis of compositional microprogram control units with modified system of microinstructions

Alexander Barkalov, Larysa Titarenko, 2008 .

Hardware Reduction in CPLD-Based Moore FSM

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, 2014, J. Circuits Syst. Comput..

Compositional microprogram control unit with operational automaton of transitions

Alexander Barkalov, Larysa Titarenko, Roman Babakov, 2013, East-West Design & Test Symposium (EWDTS 2013).

Implementing Control Algorithms with FPGAs

Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz, 2019, Foundations of Embedded Systems.

Signals and communication technology

Larysa Titarenko, Alexander Barkalov. Larysa Titarenko, 2012 .

Combining Twofold State Assignment with Transformation of Object Codes

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2020 .

Adaptation of the Two Sources of Code and One-Hot Encoding Method for Designing a Model of Microprogram Control Unit with Output Identification

Alexander Barkalov, Larysa Titarenko, Łukasz Smoliński, 2015 .

Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs

Alexander Barkalov, Larysa Titarenko, S. Chmielewski, 2019, J. Circuits Syst. Comput..

Optimization of FSMs with Embedded Memory Blocks

Alexander Barkalov, Larysa Titarenko, Valery Sklyarov, 2014 .

Distribution of Class Codes in Moore FSMs

Alexander Barkalov, Larysa Titarenko, Grzegorz Bazydlo, 2016 .

The Application and Adaptation of the Two Sources of Code and Natural Encoding Method for Designing a Model of Microprogram Control Unit with Base Structure

Alexander Barkalov, Larysa Titarenko, Łukasz Smoliński, 2014 .

Designing Moore FSM with extended class codes

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2017, 2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST).

Design of FPGA-Based Mealy FSMs with Counters

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2019, MOCAST.

Encoding of compatible micro-operations in LUT-based FSMs

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2017, Symposium on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments (WILGA).

Hardware reduction for matrix circuit of control Moore automaton

Alexander Barkalov, Larysa Titarenko, Olena Hebda, 2011, 2011 9th East-West Design & Test Symposium (EWDTS).

Design of Moore finite state machine with coding space stretching

Alexander Barkalov, Larysa Titarenko, Olena Hebda, 2014, 2014 7th International Conference on Human System Interactions (HSI).

Field Programmable Gate Arrays

Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz, 2019, Foundations of Embedded Systems.

Control Technologies in Telecommunication Systems

Alexander Barkalov, Larysa Titarenko, Vladimir Popovskij, 2011 .

Optimization of Control Memory Size of Control Unit with Codes Sharing

Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, 2007 .

Hardware reduction for RAM-based Moore FSMs

Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, 2014, 2014 7th International Conference on Human System Interactions (HSI).

Hardware Reduction for Moore EFSMs

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2018 .

Optimization of microprogram control unit with code sharing

Alexander Barkalov, Larysa Titarenko, Lukasz Smolinski, 2011, 2011 9th East-West Design & Test Symposium (EWDTS).

Object Codes Transformation for Moore FSMs

Alexander Barkalov, Larysa Titarenko, Grzegorz Bazydlo, 2016 .

Twofold State Assignment for Moore FSMs

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2020 .

Algorithms of ASSP with Not Exactly Known Parameters

Alexander Barkalov, Larysa Titarenko, A. Barkalov, 2013 .

OPTIMIZATION OF CIRCUIT OF MEALY FINITE STATE MACHINE ON FPGA BASED ON ENCODING OF THE FIELDS OF COMPATIBLE MICROOPERATIONS AND VERTICALIZATION OF FLOW-CHART

Alexander Barkalov, Larysa Titarenko, Arkadiusz Bukowiec, 2006 .

Background of Classical Theory of ASSP

Alexander Barkalov, Larysa Titarenko, A. Barkalov, 2013 .

Synthesis of control units with field-programmable logic devices

Alexander Barkalov, Larysa Titarenko, 2008 .

Foundations of Embedded Systems

Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz, 2019 .

Reduction in the number of LUT elements for control units with code sharing

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2010, Int. J. Appl. Math. Comput. Sci..

Decreasing Number of LUTs for Moore FSMs

Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki, 2019, 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems".

Synthesis of Moore FSM with encoding of collections of microoperations implemented with ASIC

Alexander Barkalov, Larysa Titarenko, O. Hebda, 2012 .

Synthesis of Moore Finite State Machines Based on Pseudoequivalent States

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, 2013, PDeS.

Hardware Reduction in FPGA-Based Moore FSM

Alexander Barkalov, Larysa Titarenko, Raisa Malcheva, 2013, J. Circuits Syst. Comput..

Optimization for Logic Circuit of Mealy FSM

Alexander Barkalov, Larysa Titarenko, 2009 .

Finite State Machines with Operational Implementation of Transitions

Alexander Barkalov, Larysa Titarenko, Valery Sklyarov, 2014 .

Hardware Reduction in Multidirectional Moore FSMs

Alexander Barkalov, Larysa Titarenko, Grzegorz Bazydlo, 2016 .

Synthesis Of Microprogram

Larysa Titarenko, Marian Adamski, Remigiusz Wisniewski, 2006 .

Twofold State Assignment for Mealy FSMs

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2020 .

Hardware Reduction for Mealy UFSMs

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2018 .

Logic Synthesis for FSM-Based Control Units

Alexander Barkalov, Larysa Titarenko, 2009, Lecture Notes in Electrical Engineering.

Synthesis of Microprogram Control Unit with Control Microinstructions

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2009 .

Synthesis of EMB - based Moore FSM with splitting set of logical conditions

Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, 2015 .

Synthesizable VHDL for FPGA-Based Devices

Alexander Barkalov, Larysa Titarenko, Valery Sklyarov, 2014 .

Synthesis of CMCU with coding of logical conditions and collections of microoperations

Alexander Barkalov, Larysa Titarenko, 2008 .

FSM Synthesis with Transformation of GSA

Alexander Barkalov, Larysa Titarenko, 2009 .

Synthesis of compositional microprogram control unit with extended microinstruction format

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.

Hardware reduction for compositional microprogram control unit dedicated for CPLD systems

Alexander Barkalov, Larysa Titarenko, Lukasz Smolinski, 2013, East-West Design & Test Symposium (EWDTS 2013).

Control and Adaptation in Telecommunication Systems - Mathematical Foundations

Alexander Barkalov, Larysa Titarenko, Vladimir Popovskij, 2011, Lecture Notes in Electrical Engineering.

Encoding of chain outputs in FPGA-based Moore FSMs

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2017, Symposium on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments (WILGA).

Synthesis of compositional microprogram control units with object transformation

Alexander Barkalov, Larysa Titarenko, 2008 .

Compositional microprogram control unit with operational automaton of transitions

Alexander Barkalov, Larysa Titarenko, Roman Babakov, 2013, EWDTS.

Code sharing in CPLD-based Moore FSMs

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2017, 2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST).

Evolution of Programmable Logic

Alexander Barkalov, Larysa Titarenko, A. Barkalov, 2009 .

Designing HFPGA-based FSMs with counters

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2017, 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems.

Design Technique Based on Hierarchical and Parallel Specifications

Alexander Barkalov, Larysa Titarenko, Valery Sklyarov, 2014 .

Methods of interpretation of control algorithms

Alexander Barkalov, Larysa Titarenko, 2008 .

Hardware reduction for EMB-based Mealy FSM

Alexander Barkalov, Larysa Titarenko, Marek Wegrzyn, 2015 .

Code sharing in FPGA-based Moore FSMs

Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, 2015 .

FSM Synthesis with Object Code Transformation

Alexander Barkalov, Larysa Titarenko, 2009 .

Research of efficiency of microprogram final-state machine with datapath of transitions

Alexander Barkalov, Larysa Titarenko, Roman Babakov, 2017, 2017 14th International Conference The Experience of Designing and Application of CAD Systems in Microelectronics (CADSM).

Combining Twofold State Assignment with Replacement of Logical Conditions

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2020 .

Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, 2010, 2010 East-West Design & Test Symposium (EWDTS).

Object Codes Transformation for Mealy FSMsObject codes transformation (OCT)

Alexander Barkalov, Larysa Titarenko, Grzegorz Bazydlo, 2016 .

Encoding of internal states in synthesis and implementation process of automata into FPGAs

Alexander Barkalov, Larysa Titarenko, Arkadiusz Bukowiec, 2009, 2009 10th International Conference - The Experience of Designing and Application of CAD Systems in Microelectronics.

Reducing hardware in FPGA-based Mealy FSM

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2017, Symposium on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments (WILGA).

IPNES - Interpreted Petri Net for Embedded Systems

Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki, 2021, KES.

Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment

Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki, 2021 .

Optimization of CMCU with Code Sharing

Alexander Barkalov, Larysa Titarenko, A. V. Baiev, 2021, Cybernetics and Systems Analysis.

Reducing LUT Count for Mealy FSMs with Transformation of States

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, 2021 .