Tom English

Delay dependent power optimisation of combinational circuits using AND-Inverter graphs

Emanuel M. Popovici, Michel P. Schellekens, Rashmi Mehrotra, 2010, 23rd IEEE International SOC Conference.

Network-on-Chip interconnect for pairing-based cryptographic IP cores

Maurice Keller, William P. Marnane, Emanuel M. Popovici, 2011, J. Syst. Archit..

A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT)

John W. Lockwood, Kees A. Vissers, Michaela Blott, 2012, 2012 IEEE 20th Annual Symposium on High-Performance Interconnects.

HotSpot : Visualizing dynamic power consumption in RTL designs

Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens, 2008, Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08).

Preface of the 2010 IAENG International Conference on Electrical Engineering Special Session: Design, Analysis and Tools for Integrated Circuits and Systems. Newswood Limited

Chee Peng Lim, Alie El-Din Mady, Jin Song Dong, 2010 .

Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for Cryptographic accelerators

Emanuel M. Popovici, Tom English, 2011, Proceedings of the Fifth ACM/IEEE International Symposium.

Timing-Driven Power Optimisation and Power-Driven Timing Optimisation of Combinational Circuits

Emanuel M. Popovici, Michel P. Schellekens, Steve Hollands, 2011, J. Low Power Electron..

A Switching Activity Analysis and visualisation tool for power optimisation of SoC buses

Ka Lok Man, Emanuel Popovici, Tom English, 2009, 2009 Ph.D. Research in Microelectronics and Electronics.

A low-power pairing-based cryptographic accelerator for embedded security applications

Maurice Keller, William P. Marnane, Ka Lok Man, 2009, 2009 IEEE International SOC Conference (SOCC).

BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation

Ka Lok Man, Emanuel M. Popovici, Tom English, 2009, PATMOS.