Horácio C. Neto

发表

Area/Performance Improvement of NoC Architectures

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2006, ARC.

An efficient and scalable architecture for neural networks with backpropagation learning

Pedro M. Domingos, Horácio C. Neto, Fernando M. Silva, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping

Horácio C. Neto, João M. P. Cardoso, Ricardo S. Ferreira, 2005, SAMOS.

A reconfigurable computing architecture using magnetic tunneling junction memories

Mário P. Véstias, Jorge R. Fernandes, Horácio C. Neto, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

An exact solution to the minimum size test pattern problem

Paulo F. Flores, Joao Marques-Silva, Horácio C. Neto, 2001, TODE.

Modeling and Simulation of a Many-core Architecture Using SystemC

Horácio C. Neto, Mario Vestias, Ana Rita Silva, 2014 .

Multi-core for K-means clustering on FPGA

Horácio C. Neto, Mario Vestias, Jose Canilho, 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

ROUTER DESIGNFOR APPLICATIONSPECIFICNETWORKS-ON-CHIPON RECONFIGURABLESYSTEMS

Horácio C. Neto, MarioP . Vestias, 2007 .

Decimal Division Using the Newton–Raphson Method and Radix-1000 Arithmetic

Horácio C. Neto, Mario Vestias, 2013 .

Fast Convolutional Neural Networks in Low Density FPGAs Using Zero-Skipping and Weight Pruning

Horácio C. Neto, Rui Policarpo Duarte, Mario Vestias, 2019, Electronics.

Efficient implementation of a single-precision floating-point arithmetic unit on FPGA

Mário P. Véstias, Horácio C. Neto, Ana Rita Silva, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions

Mário P. Véstias, Jorge R. Fernandes, Horácio C. Neto, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Document Type: Proceedings Paper

Horácio C. Neto, Helena Sarmento, 2013 .

Run-Time Reconfigurable Array Using Magnetic RAM

Mário P. Véstias, Luís Bica Oliveira, Jorge R. Fernandes, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

An Approach to Hardware Synthesis from a

Horácio C. Neto, João M. P. Cardoso, 1998 .

FPGA redundancy recovery based on partial bitstreams for multiple partitions

Horácio C. Neto, Eduardo Augusto Bezerra, Victor M. Goncalves Martins, 2015, 2015 16th Latin-American Test Symposium (LATS).

A fast and scalable architecture to run convolutional neural networks in low density FPGAs

Horácio C. Neto, Rui Policarpo Duarte, Mario Vestias, 2020, Microprocess. Microsystems.

Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs

Mário P. Véstias, Horácio C. Neto, Rui Policarpo Duarte, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

An Efficient Exact Fused Dot Product Processor in FPGA

Horácio C. Neto, Luís Fiolhais, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

Sorting Units for FPGA-Based Embedded Systems

Horácio C. Neto, João M. P. Cardoso, Rui Marcelino, 2008, DIPES.

Analysis of matrix multiplication on high density Virtex-7 FPGA

Mário P. Véstias, Horácio C. Neto, Ana Rita Silva, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

Decimal multiplier on FPGA using embedded binary multipliers

Mário P. Véstias, Horácio C. Neto, 2008, 2008 International Conference on Field Programmable Logic and Applications.

A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow

Horácio C. Neto, Eduardo Augusto Bezerra, Paulo Ricardo Cechelero Villa, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

On exponential fitting for circuit simulation

Jacob K. White, Luís Miguel Silveira, Horácio C. Neto, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers

Horácio C. Neto, Mario Vestias, 2010 .

Designing Hardware/Software Systems for Embedded High-Performance Computing pdf

Mário P. Véstias, Horácio C. Neto, Rui Policarpo Duarte, 2015, ArXiv.

Improving the area of fast parallel decimal multipliers

Mário P. Véstias, Horácio C. Neto, 2018, Microprocess. Microsystems.

K-means clustering on CGRA

Mário P. Véstias, José T. de Sousa, Horácio C. Neto, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm

Horácio C. Neto, Rui Policarpo Duarte, Helena Cruz, 2020, ARC.

Hardware Design for Decimal Multiplication

Horácio C. Neto, Mario Vestias, 2015 .

Bitwise encoding of finite state machines

José C. Monteiro, Srinivas Devadas, Horácio C. Neto, 1994, Proceedings of 7th International Conference on VLSI Design.

Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Reconfigurable Circuits Using Magnetic Tunneling Junction Memories

Jorge R. Fernandes, Horácio C. Neto, Victor Silva, 2010, DoCEIS.

Adaptive Network-on-Chip

Horácio C. Neto, Mario Vestias, 2015 .

DALI: a methodology for the co-design of dataflow applications on hardware/software architectures [video encoder DSP example]

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

Enhancing stochastic computations via process variation

Mário P. Véstias, Horácio C. Neto, Rui Policarpo Duarte, 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

Multiplier-based double precision floating point divider according to the IEEE-754 standard

Mário P. Véstias, Horácio C. Neto, Rui Policarpo Duarte, 2008, ARC.

Co-synthesis of a configurable SoC platform based on a network on chip architecture

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Revisiting the Newton-Raphson Iterative Method for Decimal Division

Mário P. Véstias, Horácio C. Neto, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Sliding block Viterbi decoders in FPGA

Mário P. Véstias, Horácio C. Neto, Helena Sarmento, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

A Many-Core Overlay for High-Performance Embedded Computing on FPGAs pdf

Mário P. Véstias, Horácio C. Neto, 2014, ArXiv.

Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation

Paulo F. Flores, José C. Monteiro, Joao Marques-Silva, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

Parallel dot-products for deep learning on FPGA

Mário P. Véstias, José T. de Sousa, Horácio C. Neto, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions

Horácio C. Neto, Eduardo Augusto Bezerra, Victor M. Goncalves Martins, 2015, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines.

An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs

Horácio C. Neto, João M. P. Cardoso, H. Neto, 1999, VLSI.

Embedded Fault-Tolerant Accelerator Architecture for Synthetic-Aperture Radar Backprojection

Horácio C. Neto, Rui Policarpo Duarte, Helena Cruz, 2019 .

Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging

Horácio C. Neto, Rui Policarpo Duarte, Helena Cruz, 2019, ARC.

Correction to: Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm

Horácio C. Neto, Rui Policarpo Duarte, Helena Cruz, 2020 .

A Co-Synthesis Environment for Embedding Digital Systems in a Sea-of-Gates IC

Horácio C. Neto, João M. P. Cardoso, 1996 .

XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system

Mário P. Véstias, Horácio C. Neto, Rui Policarpo Duarte, 2016, 2016 IEEE International Conference on Rebooting Computing (ICRC).

Stochastic Processors on FPGAs to Compute Sensor Data Towards Fault-Tolerant IoT Systems

Horácio C. Neto, Rui Policarpo Duarte, 2018, 2018 IEEE Conference on Dependable and Secure Computing (DSC).

Trends of CPU, GPU and FPGA for high-performance computing

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm

Mário P. Véstias, Horácio C. Neto, 2012, 2012 15th Euromicro Conference on Digital System Design.

Moving Deep Learning to the Edge

Horácio C. Neto, Rui Policarpo Duarte, Mario Vestias, 2020, Algorithms.

kNN-STUFF: kNN STreaming Unit for Fpgas

Horácio C. Neto, João Vieira, Rui P. Duarte, 2019, IEEE Access.

A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs

Mário P. Véstias, Horácio C. Neto, Rui P. Duarte, 2020, IEEE Access.

System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2002, Proceedings 13th IEEE International Workshop on Rapid System Prototyping.

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Mário P. Véstias, Horácio C. Neto, Ana Rita Silva, 2015 .

Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines

Horácio C. Neto, João M. P. Cardoso, 2001, FPL.

Test pattern generation for width compression in BIST

Paulo F. Flores, Joao Marques-Silva, Horácio C. Neto, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory

Mário P. Véstias, Jorge R. Fernandes, Horácio C. Neto, 2012, 2012 International Conference on Reconfigurable Computing and FPGAs.

FPGA-based OpenCL Accelerator for Discovering Temporal Patterns in Gene Expression Data Using Biclustering

Horácio C. Neto, Rui Henriques, Rui Policarpo Duarte, 2018, PBio 2018.

Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system

Horácio C. Neto, João M. P. Cardoso, H. Neto, 1999, Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387).

Macro-based hardware compilation of Java/sup TM/ bytecodes into a dynamic reconfigurable computing system

Horácio C. Neto, João M. P. Cardoso, H. Neto, 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs

Mário P. Véstias, Horácio C. Neto, Helena Sarmento, 2012, 2012 15th Euromicro Conference on Digital System Design.

A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2006, 2006 International Conference on Field Programmable Logic and Applications.

An exact solution to the minimum size test pattern problem

Paulo F. Flores, Joao Marques-Silva, Horácio C. Neto, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Decimal addition on FPGA based on a mixed BCD/excess-6 representation

Mário P. Véstias, Horácio C. Neto, 2017, Microprocess. Microsystems.

Exploiting Don't Car es in Test Patterns to Reduce Power During BIST

José Monteiro, Horácio C. Neto, José Carlos Costa, 1998 .

An Environment for Exploring Data-Driven Architectures

Horácio C. Neto, João M. P. Cardoso, Ricardo S. Ferreira, 2004, FPL.

On applying set covering models to test set compaction

Paulo F. Flores, Horácio C. Neto, João P. Marques-Silva, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture

Mário P. Véstias, Horácio C. Neto, Wilson Jose, 2015, 2015 Euromicro Conference on Digital System Design.

Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs

Mário P. Véstias, José T. de Sousa, Horácio C. Neto, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

Very low resource table-based FPGA evaluation of elementary functions

Mário P. Véstias, Horácio C. Neto, 2013, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig).

Area and performance optimization of a generic network-on-chip architecture

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2006, SBCCI '06.

Unbalanced FIFO sorting for FPGA-based systems

Horácio C. Neto, João M. P. Cardoso, Rui Marcelino, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA

Mário P. Véstias, José T. de Sousa, Horácio C. Neto, 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

On Reconfigurable Architectures for Efficient Matrix Inversion

Horácio C. Neto, Goncalo M. de Matos, H. Neto, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Coarse-Grained Reconfigurable Computing with the Versat Architecture

Mário P. Véstias, Horácio C. Neto, João D. Lopes, 2021 .

A Full Featured Configurable Accelerator for Object Detection With YOLO

Mário P. Véstias, Horácio C. Neto, João D. Lopes, 2021, IEEE Access.

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Mário P. Véstias, Horácio C. Neto, 2021, Algorithms.

Configurable Hardware Core for IoT Object Detection

Mário P. Véstias, José T. de Sousa, Horácio C. Neto, 2021, Future Internet.

A Model and Algorithm for Computing Minimum-Size Test Patterns

Krishnendu Chakrabarty, Horácio C. Neto, Paulo Flores, 1998 .