Tetsushi Koide

发表

Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size

Hans Jürgen Mattausch, Tetsushi Koide, R. Kimura, 2010, 2010 First International Conference on Networking and Computing.

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC

Hans Jürgen Mattausch, Kazutami Arimoto, Katsumi Dosaka, 2006, IEICE Trans. Electron..

350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node

Hans Jurgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2004 .

Combined Data/Instruction Cache with Bank-Based Multi-Port Architecture

Hans Jurgen Mattausch, Tetsuo Hironaka, Tetsushi Koide, 2003 .

Application of Multi-ported CAM for Parallel Coding

Hans Jürgen Mattausch, Takeshi Kumaki, Tetsushi Koide, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory

Hans Jürgen Mattausch, Takeshi Kumaki, Tetsushi Koide, 2007, IEICE Trans. Inf. Syst..

Automatic Pattern-Learning Architecture Based on Associative Memory and Short/Long Term Storage Concept

Hans Jurgen Mattausch, Tetsushi Koide, Yoshinori Shirakawa, 2004 .

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2007, IEICE Trans. Inf. Syst..

SVM-MRF segmentation of colorectal NBI endoscopic images

Shinji Tanaka, Kazufumi Kaneda, Tetsushi Koide, 2014, 2014 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society.

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh

Hans Jürgen Mattausch, Kazutami Arimoto, Kazuyasu Fujishima, 2005, IEICE Trans. Electron..

A scalable massively parallel processor for real-time image processing

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A parallel genetic algorithm with adaptive adjustment of genetic parameters

Shin'ichi Wakabayashi, Tetsushi Koide, Isao Nishimura, 2001 .

Low cost hardware implementation for traffic sign detection system

Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding

Hans Jürgen Mattausch, Akio Kawabata, Tetsushi Koide, 2010, 2010 First International Conference on Networking and Computing.

Compact hardware oriented number recognition algorithm for real-time speed traffic-sign recognition

Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Transfer Learning for Endoscopic Image Classification pdf

Shinji Tanaka, Kazufumi Kaneda, Tetsushi Koide, 2016, ArXiv.

A new system partitioning method under performance and physical constraints for multi-chip modules

Shin'ichi Wakabayashi, Tetsushi Koide, Yoshinori Katsura, 1995, ASP-DAC '95.

A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout

Shin'ichi Wakabayashi, Tetsushi Koide, T. Koide, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

A new performance driven placement method with the Elmore delay model for row based VLSIs

Shin'ichi Wakabayashi, Tetsushi Koide, Mitsuhiro Ono, 1995, ASP-DAC '95.

Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual

Shin'ichi Wakabayashi, Tetsushi Koide, Koichi Hatta, 2001 .

Methode und System zum Erkennen und Erlernen von Referenzdaten

Tetsushi Koide, Masahiro Mizokami, Hans-Jürgen Mattausch, 2004 .

Path Encoding Method for High Speed Frequency-Mapping Associative Memory

Akio Kawabata, Tetsushi Koide, Masahiro Yasuda, 2011 .

A Hardware Implementation of Colorectal Tumor Classification for Endoscopic Video on Customizable DSP Toward Real-Time Computer-Aided Diagnosis System

Takumi Okamoto, Shinji Tanaka, Kazufumi Kaneda, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Mixed Planar and H-V Over-the-Cell Routing for Standard Cells with Nonuniform Over-the-Cell Routing Capacities (Special Issue on Synthesis and Verification of Hardware Design)

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1996 .

A Hardware Implementation on Customizable Embedded DSP Core for Colorectal Tumor Classification with Endoscopic Video toward Real-Time Computer-Aided Diagnosis System

Takumi Okamoto, Kazufumi Kaneda, Tetsushi Koide, 2020 .

A verification algorithm for logic circuits with internal variables

Tetsushi Koide, Noriyoshi Yoshida, Toshihiro Nakaoa, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Chip size and performance evaluations of shared cache for on-chip multiprocessor

Takahiro Sasaki, Tetsuo Hironaka, Hans Jürgen Mattausch, 2005, Systems and Computers in Japan.

Pipeline scanning architecture with computation reduction for rectangle pattern matching in real-time traffic sign detection

Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Smoothing posterior probabilities with a particle filter of dirichlet distribution for stabilizing colorectal NBI endoscopy recognition

Shinji Tanaka, Kazufumi Kaneda, Tetsushi Koide, 2013, 2013 IEEE International Conference on Image Processing.

Real-time hybrid learning and recognition system with software-hardware cooperation

Fengwei An, Hans Jürgen Mattausch, Tetsushi Koide, 2011, 2011 IEEE International Conference on Robotics and Biomimetics.

A Hardware-Based Genetic Algorithm with Adaptive Selection of Crossover Operators:LSI Implementation and Its Evaluation

Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, 1998 .

A Hierarchical Standard-Cell Placement Method Based on Wire Length-Driven Clustering

Wakabayashi Shin'ichi, Toshio Tsuji, Hajime Kubota, 2003 .

A systolic graph partitioning algorithm for VLSI design

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture

Hans Jurgen Mattausch, Tetsushi Koide, Keita Okazaki, 2009 .

Developing aReliable Learning ModelforCognitive Classification Tasks Using anAssociative Memory

Tetsushi Koide, Yoshinori Shirakawa, HansJuirgen Mattausch, 2007 .

Construction and Evaluation of Bank - based Multi - port Memory using Blocking Network

Takahiro Sasaki, Tetsuo Hironaka, Tetsushi Koide, 2003 .

Labeling colorectal NBI zoom-videoendoscope image sequences with MRF and SVM

Shinji Tanaka, Kazufumi Kaneda, Tetsushi Koide, 2013, 2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Digital Gray-Scale/Color Image-Segmentation Architecture for Cell-Network-Based Real-Time Applications

Hans Jurgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2002 .

Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories

Hans Jürgen Mattausch, Yuki Tanaka, Ali Ahmadi, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Development of a Real-time Colorectal Tumor Classification System for Narrow-band Imaging zoom-videoendoscopy pdf

Shinji Tanaka, Kazufumi Kaneda, Tetsushi Koide, 2016, ArXiv.

A Timing-Driven Hierarchical Global Routing Method with Buffer-Insertion and Wire-Sizing for Multi-Layer ULSI

Shin'ichi Wakabayashi, Tetsushi Koide, Takahiro Deguchi, 1999 .

A Graph Bisection Algorithm Based on Subgraph Migration (Special Section on VLSI Design and CAD Algorithms)

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1994 .

An associative memory-based learning model with an efficient hardware implementation in FPGA

Hans Jürgen Mattausch, Ali Ahmadi, Tetsushi Koide, 2011, Expert Syst. Appl..

Real-time Speed Limit Traffic Sign Detection System for Robust Automotive Environments

Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto, 2015 .

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Keynote 1: The Role of Functional Memories in Parallel Information Processing with Localized and Distributed Systems

Takeshi Kumaki, Tetsushi Koide, Koh Johguchi, 2010, PDCAT 2010.

An IoT-gateway with the information-centric communication

Takumi Okamoto, Atsushi Hirota, Tetsushi Koide, 2019, 2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS).

A new global routing algorithm for over-the-cell routing in standard cell layouts

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs

Shin'ichi Wakabayashi, Tetsushi Koide, Mitsuhiro Ono, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications

Hans Jurgen Mattausch, Tetsushi Koide, Yuji Yano, 2004 .

Feature Extraction of Colorectal Endoscopic Images for Computer-Aided Diagnosis with CNN

Takumi Okamoto, Shinji Tanaka, Kazufumi Kaneda, 2019, 2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS).

Bank-Type Multiport Register File for Highly-Parallel Processors

Hans Jurgen Mattausch, Tetsuo Hironaka, Tetsushi Koide, 2003 .

A floorplanning method with topological constraint manipulation

Shin'ichi Wakabayashi, Tetsushi Koide, Yoshinori Katsura, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems

Hans Jürgen Mattausch, Takeshi Kumaki, Tetsushi Koide, 2011, IEICE Trans. Inf. Syst..

Gate array placement based on mincut partitioning with path delay constraints

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1993, 1993 IEEE International Symposium on Circuits and Systems.

An optimal channel pin assignment with multiple intervals for building block layout

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

Digital Low-Power Real-Time Video Segmentation by Region Growing

Hans Jurgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2004 .

Associative memory with fully parallel nearest-manhattan-distance search for low-power real-time single-chip applications

Hans Jürgen Mattausch, Tetsushi Koide, Yuji Yano, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2007, IEICE Trans. Inf. Syst..

Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

Shin'ichi Wakabayashi, Tetsushi Koide, Takahiro Deguchi, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2008, IEICE Trans. Electron..

4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words

Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide, 2007, IEICE Trans. Electron..

A Fully-Parallel Associative Memory for Minimum-Manhattan-Distance-Search

Hans Jurgen Mattausch, Tetsushi Koide, Yuji Yano, 2002 .

Solving the rectangular packing problem by an adaptive GA based on sequence-pair

Shin'ichi Wakabayashi, Tetsushi Koide, Koichi Hatta, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

CMOS Test Chip for a High-Speed Digital Image-Segmentation Architecture with Pixel-Parallel Processing

Hans Jurgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2003 .

FPGA implementation of feature extraction for colorectal endoscopic images with NBI magnification

Anh-Tuan Hoang, Shinji Tanaka, Kazufumi Kaneda, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Domain Adaptation with L2 constraints for classifying images from different endoscope systems pdf

Shinji Tanaka, Kazufumi Kaneda, Takio Kurita, 2016, ArXiv.

Three-layer channel routing for standard cells with column-dependent variable over-the-cell routing capacities

Masahiro Tsuchiya, Tetsushi Koide, S. Wakabayashi, 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

A three-layer over-the-cell multi-channel router for a new cell model

Masahiro Tsuchiya, Shin'ichi Wakabayashi, Tetsushi Koide, 1996, Integr..

An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1997, Integr..

Distributed crossbar architecture for area-efficient combined data/instruction caches with multiple ports

Hans Jurgen Mattausch, Tetsushi Koide, Koh Johguchi, 2004 .

A Rectilinear Steiner Tree Construction Algorithm with Simultaneous Buffer Insertion and Wire Sizing

Shin'ichi Wakabayashi, Tetsushi Koide, Kosuke Ogama, 1998 .

Mechanochemistry at the Single Bond Limit: Towards `Deterministic Epitaxy'

Shinji Tanaka, Tetsushi Koide, Bisser Raytchev, 2014 .

Performance evaluation of superscalar processor with multi-bank register file using SPEC2000

Hans Jurgen Mattausch, Tetsuo Hironaka, Tetsushi Koide, 2006 .

procédé et dispositif pour reconnaitre et apprendre des data de reference

Tetsushi Koide, Masahiro Mizokami, Hans-Jürgen Mattausch, 2004 .

A study of compact and multi-banks memory suitable for LSI

Takahiro Sasaki, Tetsuo Hironaka, Tetsushi Koide, 2002 .

Parallel hardware design for snake models with an FPGA architecture

Hans Jurgen Mattausch, Tetsushi Koide, Ali Ahmadi, 2005 .

A three-layer over-the-cell multi-channel routing method for a new cell model

Masahiro Tsuchiya, Shin'ichi Wakabayashi, Tetsushi Koide, 1995, ASP-DAC '95.

A parallel hardware design for parametric active contour models

Hans Jürgen Mattausch, Ali Ahmadi, Tetsushi Koide, 2005, IEEE Conference on Advanced Video and Signal Based Surveillance, 2005..

Discriminative Subtree Selection for NBI Endoscopic Image Labeling

Shinji Tanaka, Kazufumi Kaneda, Takio Kurita, 2016, ACCV Workshops.

Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline

Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm

Shin'ichi Wakabayashi, Tetsushi Koide, Koichi Hatta, 1998, PPSN.

A timing-driven floorplanning algorithm with the Elmore delay model for building block layout

Shin'ichi Wakabayashi, Tetsushi Koide, 1999, Integr..

A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA

Hans Jürgen Mattausch, Ali Ahmadi, Tetsushi Koide, 2006, 2006 IEEE International Conference on Evolutionary Computation.

Multi-Port-Cache Design with Hierarchical Multi-Bank Memory

Hans Jurgen Mattausch, Tetsuo Hironaka, Tetsushi Koide, 2002 .

Pipeline Scanning Architecture for Traffic Sign Detection with Computation Reduction (コンピュータシステム)

Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto, 2013 .

Low-Complexity, Highly-Parallel Color Motion-Picture Segmentation Architecture for Compact Digital CMOS Implementation

Hans Jurgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2002 .

Pin assignment with global routing for VLSI building block layout

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An Efficient Timing-Driven Global Routing Method for Standard Cell Layout (Special Issue on Synthesis and Verification of Hardware Design)

Shin'ichi Wakabayashi, Tetsushi Koide, Takeshi Suzuki, 1996 .

Image-Scan Architecture for Efficient FPGA/ASIC Implementation of Video-Segmentation by Region Growing

Hans Jurgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2005 .

A performance-driven global routing algorithm with wire-sizing and buffer-insertion

Shin'ichi Wakabayashi, Tetsushi Koide, Takahiro Deguchi, 1998, IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242).

Effective Diagnostic Image Segmentation with Pyramid Style Support Vector Machine for Colorectal Endoscopic Images

Anh-Tuan Hoang, Takumi Okamoto, Kazufumi Kaneda, 2015 .

Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Application of Bank-Based Multiport Memory to the Microprocessor Caches

Hans Jurgen Mattausch, Tetsuo Hironaka, Tetsushi Koide, 2005 .

Compact 12-port multi-bank register file test-chip in 0.35/spl mu/m CMOS for highly parallel processors

Hans Jurgen Mattausch, Tetsuo Hironaka, Tetsushi Koide, 2004 .

A Floorplanning Method for Simultaneously Determining Module Placement and Global Routes Considering Buffer Insertion

Wakabayashi Shin'ichi, Tetsushi Koide, Shingo Nakaya, 2000 .

Image segmentation of pyramid style identifier based on Support Vector Machine for colorectal endoscopic images

Anh-Tuan Hoang, Takumi Okamoto, Shinji Tanaka, 2015, 2015 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

A 381 fs/bit, 51.7 nW/bit nearest hamming-distance search circuit in 65 nm CMOS

Akio Kawabata, Tetsushi Koide, Masahiro Yasuda, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features

Hans Jürgen Mattausch, Kazutami Arimoto, Tetsushi Koide, 2005, IEICE Trans. Electron..

Pixel-parallel digital CMOS implementation of image segmentation by region growing

Hans Jurgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2005 .

Topological optimization with a network reliability constraint

Tetsushi Koide, H. Ishii, S. Shinmori, 2001, Discret. Appl. Math..

Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual

Shin'ichi Wakabayashi, Tetsushi Koide, Koichi Hatta, 2001, Systems and Computers in Japan.

Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping

Hans Jürgen Mattausch, Akio Kawabata, Tetsushi Koide, 2012, IEEE Journal of Solid-State Circuits.

Mixed Digital–Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search

Hans Jurgen Mattausch, Yuki Tanaka, Tetsushi Koide, 2007 .

An Image Analysis Method for Lettuce Leaf and Root Growth Analysis in Hydroponic Culture

Takumi Okamoto, Ken Kimura, Tetsushi Koide, 2018, TENCON 2018 - 2018 IEEE Region 10 Conference.

Simple Yet Effective Two-Stage Speed Traffic Sign Recognition for Robust Vehicle Environments

Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto, 2015 .

Proposition and Evaluation of a Bank based Multi-port Memory with Blocking Network

Takahiro Sasaki, Tetsuo Hironaka, Tetsushi Koide, 2004 .

An MCM routing algorithm considering crosstalk

Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Implementation of Computer-Aided Diagnosis System on Customizable DSP Core for Colorectal Endoscopic Images with CNN Features and SVM

Takumi Okamoto, Shinji Tanaka, Kazufumi Kaneda, 2018, TENCON 2018 - 2018 IEEE Region 10 Conference.

GAA: a VLSI genetic algorithm accelerator with on-the-fly adaptation of crossover operators

Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

An integrated approach to pin assignment and global routing for VLSI building-block layout

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2006, IEICE Trans. Inf. Syst..

Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

Shin'ichi Wakabayashi, Tetsushi Koide, Takahiro Deguchi, 2000, ASP-DAC '00.

Real-time segmentation architecture of gray-scale/color motion pictures and digital test-chip implementation

Hans Jurgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition

Shinji Tanaka, Kazufumi Kaneda, Tetsushi Koide, 2016, Artif. Intell. Medicine.

Genetic algorithm accelerator GAA-II

Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Acceleration of arithmetic processing with CAM-based massive-parallel SIMD matrix core

Takeshi Kumaki, Tetsushi Koide, Kyosuke Kageyama, 2020, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS).

Transfer learning for Bag-of-Visual words approach to NBI endoscopic image classification

Shinji Tanaka, Kazufumi Kaneda, Takio Kurita, 2015, 2015 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Trade-off between speed and performance for colorectal endoscopic NBI image classification

Shinji Tanaka, Kazufumi Kaneda, Tetsushi Koide, 2015, Medical Imaging.

Corrigendum to "Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition" [Artif. Intell. Med. 68 (March 2016) 1-16]

Shinji Tanaka, Kazufumi Kaneda, Tetsushi Koide, 2016, Artif. Intell. Medicine.

CAMを付加した超並列SIMDプロセッサによるAES処理高速化手法 (1) : 暗号化方法

Hans Jurgen Mattausch, Takeshi Kumaki, Tetsushi Koide, 2007 .

A low-power video segmentation LSI with boundary-active-only architecture

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2005, ASP-DAC.

Distributed against centralised crossbar function for realising bank-based multiport memories

Hans Jurgen Mattausch, Tetsushi Koide, S. Fukae, 2004 .

Compact 12-port multi-bank register file test-chip in 0.35/spl mu/m CMOS for highly parallel processors

Tetsuo Hironaka, Hans Jürgen Mattausch, Hiroshi Uchida, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Bank-Type Associative Memory for High-Speed Nearest Manhattan Distance Search in Large Reference-Pattern Space

Hans Jurgen Mattausch, Tetsushi Koide, Yuji Yano, 2004 .

Fully Parallel Nearest Manhattan-Distance-Search Memory With Large Reference-Pattern Number

Hans Jurgen Mattausch, Tetsushi Koide, Yuji Yano, 2002 .

Structuring Element-counting Approach for Morphological Pattern Spectrum-based Image Manipulation Detection

Takeshi Kumaki, Tetsushi Koide, Kyosuke Kageyama, 2019, 2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS).

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching

Fengwei An, Hans Jürgen Mattausch, Tetsushi Koide, 2012, IEICE Trans. Inf. Syst..

Evaluation of bank-based multiport memory architecture with blocking network

Hans Jurgen Mattausch, Takahiro Sasaki, Tetsuo Hironaka, 2006 .

Multi-object tracking VLSI architecture using image-scan based region growing and feature matching

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Measurement-Based Ring Oscillator Variation Analysis

Hans Jürgen Mattausch, Tetsushi Koide, Norio Sadachika, 2010, IEEE Design & Test of Computers.

An FPGA-implemented Associative-memory Based Online Learning Method

Fengwei An, Hans Jurgen Mattausch, Tetsushi Koide, 2011 .

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

Takeshi Kumaki, Takeshi Fujino, Tetsushi Koide, 2017 .

Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2004, IEICE Trans. Inf. Syst..

A Fault-Tolerant Distributed Mutual Exclusion Algorithm with Arbitrary Failures and Recoveries

Shin'ichi Wakabayashi, Tetsushi Koide, Shigeki Takekawa, 1996 .

Visual-Word Feature Transformation Architecture for Computer-Aided Diagnosis using Colorectal Endoscopic Images with NBI Magnification

Anh-Tuan Hoang, Takumi Okamoto, Shinji Tanaka, 2014 .

A RISC processor for high-speed execution of genetic algorithms

Shin'ichi Wakabayashi, Tetsushi Koide, Shinya Koizumi, 2001 .

Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping

Akio Kawabata, Tetsushi Koide, Hans Jurgen Mattausch, 2010, 2010 Proceedings of ESSCIRC.

Root growth detection with a sound wave-based simple measurement method: : Comparison verification with the visualization image of root growth

Tetsushi Koide, Atsushi Ogawa, Ryo Miyake, 2019 .

Power electronics education using the integrated circuit consistent education system and TCAD

Tetsushi Koide, Takeshi Tanaka, Keisuke Konishi, 2013, 2013 IEEE Frontiers in Education Conference (FIE).

A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin

Hans Jürgen Mattausch, Tetsushi Koide, Koh Johguchi, 2007, IEICE Electron. Express.

Nearest-Euclidean-Distance Search Associative Memory with Fully Parallel Mixed Digital-Analog Match Circuitry

Hans Jurgen Mattausch, Yuki Tanaka, Tetsushi Koide, 2006 .

Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor

Takeshi Kumaki, Takeshi Fujino, Tetsushi Koide, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search

Hans Jürgen Mattausch, Yuki Tanaka, Ali Ahmadi, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

A Scalable Massively Parallel Processor for Real-Time Image Processing

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2011, IEEE J. Solid State Circuits.

Object tracking in video pictures based on image segmentation and pattern matching

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance

Hans Jurgen Mattausch, T. Gyohten, Tetsushi Koide, 2002, IEEE J. Solid State Circuits.

Highly Parallel Huffman Encoding by Exploiting Multiple-Matches in Content Addressable Memory

Hans Jurgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2005 .

with Hierarchical Searching and Shift Redundancy Architecture

Hans Jurgen Mattausch, Kazutami Arimoto, Katsumi Dosaka, 2004 .

A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time

Shin'ichi Wakabayashi, Tetsushi Koide, Shigeki Takekawa, 2002, Systems and Computers in Japan.

Realization of efficient and low-power parallel face-detection with massive-parallel memory-embedded SIMD matrix

Takeshi Kumaki, Tetsushi Koide, Yuta Imai, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

Performance Driven Standard Cell Placement Based on Nonlinear Programming

Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida, 1994 .

Design of superscalar processor with multi-bank register file

Tetsuo Hironaka, Hans Jürgen Mattausch, Tadashi Saito, 2005, 2005 IEEE International Symposium on Circuits and Systems.

CAMを付加した超並列SIMDプロセッサによるAES処理高速化手法 (2) : 復号化方法

Hans Jurgen Mattausch, Takeshi Kumaki, Tetsushi Koide, 2007 .

FPGA implementation of type identifier for colorectal endoscopie images with NBI magnification

Anh-Tuan Hoang, Takumi Okamoto, Shinji Tanaka, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Low-Power Real-Time Region-Growing Image-Segmentation in 0.35μm CMOS due to Subdivided-Image and Boundary-Active-Only Architectures

Hans Jurgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2003 .

Evolution of Non - Numerical Computation performance by Integration of Instruction and Trace Cache

Tetsuo Hironaka, Tetsushi Koide, Koh Johguchi, 2003 .

Chip size and performance evaluations of shared cache for on-chip multiprocessor

Hans Jurgen Mattausch, Takahiro Sasaki, Tetsuo Hironaka, 2005 .

A standard cell global routing algorithm with net selection for over-the-cell routing

Shin'ichi Wakabayashi, Tetsushi Koide, Takeshi Suzuki, 1995 .

An LSI implementation of an adaptive genetic algorithm with on-the-fly crossover operator selection

Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Multi1-Object Tracklng VLSIArch'itecture UslngImage-Scan basedReglonGrowingandFeatureMatching

Tetsushi Koide, Takashi Morimoto, K. Awane, 2006 .

A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry

Hans Jürgen Mattausch, Tetsushi Koide, Yuji Yano, 2003, ASP-DAC '03.

On-the-fly crossover adaptation of genetic algorithms

Shin'ichi Wakabayashi, Tetsushi Koide, Koichi Hatta, 1997 .

Development of In-situ Monitoring System for Crop Growth Observation

Takumi Okamoto, Yoshiki Tanaka, Tetsushi Koide, 2019, 2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS).

Parallel Processing of Morphological Pattern Spectrum for a Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1

Takeshi Kumaki, Tetsushi Koide, Kyosuke Kageyama, 2019 .

Low Cost and Robust Field-Deployable Environmental Sensor for Smart Agriculture

Tetsushi Koide, Ryo Miyake, Yoshishige Endo, 2019, 2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS).

Low power and area efficient image segmentation VLSI architecture using 2-dimensional pixel-block scanning

Tetsushi Koide, Hans Jurgen Mattausch, Keita Okazaki, 2009, 2008 International Symposium on Intelligent Signal Processing and Communications Systems.

A Hierarchical 512-Kbit SRAM with 8 Read/Write Ports in 130nm CMOS

Hans Jurgen Mattausch, Tetsuo Hironaka, Tetsushi Koide, 2003 .

A Study on Timing-Driven Placement and Routing Algorithms in VLSI Layout Design

Tetsushi Koide, T. Koide, 2014 .

Feasibility Study for Computer-Aided Diagnosis System with Navigation Function of Clear Region for Real-Time Endoscopic Video Image on Customizable Embedded DSP Cores

Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, 2021, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.

Sweat Droplets Detection Using Image Segmentation on Skin Surface for Evaluation of Sweating Responses to Thermal Stimulus in Atopic Dermatitis

Tetsushi Koide, Ryuichi Michida, Seiji Izakura, 2021, 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS).

An Image Segmentation Method for Automatic Analysis of Skin Surface Structure in Atopic Dermatitis by the Impression Mold Technique

Tetsushi Koide, Ryuichi Michida, Seiji Izakura, 2021, 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS).

Compact Pipeline Hardware Architecture for Pattern Matching on Real-Time Traffic Signs Detection

Anh-Tuan Hoang, Tetsushi Koide, Mutsumi Omori, 2013 .

Speed Traffic-Sign Recognition Algorithm for Real-Time Driving Assistant System

Anh-Tuan Hoang, Tetsushi Koide, Mutsumi Omori, 2013 .

A Performance-Driven Floorplanning Method with Interconnect Performance Estimation

Shin'ichi Wakabayashi, Tetsushi Koide, Shingo Nakaya, 2002, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Method of Image Analysis for Leaf and Root Growth Monitoring in Lettuce Hydroponic Culture

Tetsushi Koide, 2017 .

An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints

Shin'ichi Wakabayashi, Tetsushi Koide, T. Koide, 2000 .

Within-Die/Wafer Variation Analysis of Basic CMOS Circuits based on Surface-Potential-Model HiSIM2

Tetsushi Koide, Norio Sadachika, Koh Johguchi, 2009 .

Customizable Hardware Architecture of Support Vector Machine in CAD System for Colorectal Endoscopic Images with NBI Magnification

Anh-Tuan Hoang, Shinji Tanaka, Kazufumi Kaneda, 2013 .