Shobha Vasudevan

发表

Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems

Jacob A. Abraham, Shobha Vasudevan, Vinod Viswanath, 2007, IEEE Transactions on Computers.

Goal-oriented stimulus generation for analog circuits

Shobha Vasudevan, Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, 2012, DAC Design Automation Conference 2012.

A figure of merit for assertions in verification

Shobha Vasudevan, Sam Hertz, Debjit Pal, 2019, ASP-DAC.

Efficient validation input generation in RTL by hybridized source code analysis

Shobha Vasudevan, Lingyi Liu, Lingyi Liu, 2011, 2011 Design, Automation & Test in Europe.

PRECIS: Inferring invariants using program path guided clustering

Shobha Vasudevan, Parth Sagdeo, Viraj Athavale, 2011, 2011 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011).

SHARPE: Variation-Aware Formal Statistical Timing Analysis in RTL

Shobha Vasudevan, Jayanand Asok Kumar, 2009 .

Formal Probabilistic Timing Verification in RTL

Shobha Vasudevan, Jayanand Asok Kumar, Shobha Vasudevan, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Runtime verification of nonlinear analog circuits using incremental Time-augmented RRT algorithm

Shobha Vasudevan, Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Generating concise assertions with complete coverage

Shobha Vasudevan, Chen-Hsuan Lin, Lingyi Liu, 2013, GLSVLSI '13.

Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft Errors

Shobha Vasudevan, Elyse Rosenbaum, Keven Feng, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Towards coverage closure: Using GoldMine assertions for generating design validation stimulus

Shobha Vasudevan, William Tuohy, Lingyi Liu, 2011, 2011 Design, Automation & Test in Europe.

Using static analysis for coverage extraction fromemulation/prototyping platforms

Shobha Vasudevan, Sam Hertz, Viraj Athavale, 2012, CODES+ISSS '12.

Application Level Hardware Tracing for Scaling Post-Silicon Debug

Sandip Ray, Shobha Vasudevan, Abhishek Sharma, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

Application level hardware tracing for scaling post-silicon debug

Sandip Ray, Flavio M. de Paula, Shobha Vasudevan, 2018, DAC.

Diagnosing root causes of system level performance violations

Shobha Vasudevan, Lingyi Liu, Xiaotao Chen, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Application level investigation of system-level ESD-induced soft failures

Shobha Vasudevan, Elyse Rosenbaum, Rui Jiang, 2016, 2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Static program transformations for efficient software model checking

Jacob A. Abraham, Shobha Vasudevan, J. Abraham, 2004, IFIP Congress Topical Sessions.

Automatic Verification of Arithmetic Circuits in RTL using Term Rewriting Systems

Shobha Vasudevan, S. Vasudevan, 2003 .

Automatic Generation of System Level Assertions from Transaction Level Models

Shobha Vasudevan, Lingyi Liu, 2013, J. Electron. Test..

Hardware and Software Combined Detection of SystemLevel ESD-Induced Soft Failures

Shobha Vasudevan, Yang Xiu, Elyse Rosenbaum, 2018, 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Verifying dynamic power management schemes using statistical model checking

Shobha Vasudevan, Jayanand Asok Kumar, Shobha Vasudevan, 2012, 17th Asia and South Pacific Design Automation Conference.

Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL

Jacob A. Abraham, Shobha Vasudevan, Vinod Viswanath, 2009, 2009 22nd International Conference on VLSI Design.

GoldMine: Automatic assertion generation using data mining and static analysis

David Tcheng, Sanjay J. Patel, Shobha Vasudevan, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTL

Shobha Vasudevan, Lingyi Liu, Lingyi Liu, 2014, TODE.

Packer classifier based on PE header information

Shobha Vasudevan, Michael Bailey, Qiao Jin, 2015, HotSoS.

Variation-Conscious Formal Timing Verification in RTL

Shobha Vasudevan, Jayanand Asok Kumar, Shobha Vasudevan, 2011, 2011 24th Internatioal Conference on VLSI Design.

Statistical guarantees of performance for MIMO designs

Shobha Vasudevan, Jayanand Asok Kumar, Shobha Vasudevan, 2010, 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN).

Reachability analysis of nonlinear analog circuits through iterative reachable set reduction

Shobha Vasudevan, Seyed Nematollah Ahmadyan, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Word level feature discovery to enhance quality of assertion mining

Shobha Vasudevan, Chen-Hsuan Lin, Lingyi Liu, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Automatic Generation of High Coverage Transient Fault Detectors Using GoldMine

Shobha Vasudevan, Viraj Athavale, 2011 .

Fast eye diagram analysis for high-speed CMOS circuits

Chenjie Gu, Shobha Vasudevan, Eli Chiprout, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Using automatically generated invariants for regression testing and bug localization

Shobha Vasudevan, Debjit Pal, Parth Sagdeo, 2013, 2013 28th IEEE/ACM International Conference on Automated Software Engineering (ASE).

A scalable approach for throughput estimation of timing speculation designs

Shobha Vasudevan, Viraj Athavale, Jayanand Asok Kumar, 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs

Shobha Vasudevan, Jayanand Asok Kumar, Shobha Vasudevan, 2010, 2010 Seventh International Conference on the Quantitative Evaluation of Systems.

A Technique for Test Coverage Closure Using GoldMine

Shobha Vasudevan, William Tuohy, Lingyi Liu, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Evaluating Code Coverage of Assertions by Static Analysis of RTL

Shobha Vasudevan, Viraj Athavale, Samuel Hertz, 2011 .

High level static analysis of system descriptions for taming verification complexity

Jacob A. Abraham, Shobha Vasudevan, J. Abraham, 2007 .

Can't see the forest for the trees: State restoration's limitations in post-silicon trace signal selection

Sandip Ray, Rui Jiang, Shobha Vasudevan, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Every test makes a difference: Compressing analog tests to decrease production costs

Shobha Vasudevan, Suriyaprakash Natarajan, Seyed Nematollah Ahmadyan, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

A novel test compression algorithm for analog circuits to decrease production costs

Shobha Vasudevan, Suriyaprakash Natarajan, Seyed Nematollah Ahmadyan, 2017, Integr..

Still a Fight to Get It Right: Verification in the Era of Machine Learning

Shobha Vasudevan, Shobha Vasudevan, 2017, 2017 IEEE International Conference on Rebooting Computing (ICRC).

Emphasizing Functional Relevance Over State Restoration in Post-Silicon Signal Tracing

Shobha Vasudevan, Debjit Pal, Sai Ma, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Sequential equivalence checking between system level and RTL descriptions

Jacob A. Abraham, Shobha Vasudevan, Vinod Viswanath, 2008, Des. Autom. Embed. Syst..

Gene Sets Analysis using Network Patterns

Charles Blatti, Krishna R. Kalari, Shobha Vasudevan, 2019, bioRxiv.

Automated Transient Input Stimuli Generation for Analog Circuits

Shobha Vasudevan, Seyed Nematollah Adel Ahmadyan, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Coverage Guided Mining Approach for Automatic Generation of Succinct Assertions

Shobha Vasudevan, Lingyi Liu, David Sheridan, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor

Jacob A. Abraham, Shobha Vasudevan, Sankar Gurumurthy, 2006, 2006 IEEE International Test Conference.

Symptomatic Bug Localization for Functional Debug of Hardware Designs

Shobha Vasudevan, Debjit Pal, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level

Jacob A. Abraham, Shobha Vasudevan, Vinod Viswanath, 2009, J. Low Power Electron..

Scaling RTL property checking using feasible path analysisand decomposition

Shobha Vasudevan, Lingyi Liu, 2013, GLSVLSI '13.

Signature Pattern Covering via Local Greedy Algorithm and Pattern Shrink

Jiawei Han, Tarek F. Abdelzaher, Shobha Vasudevan, 2011, 2011 IEEE 11th International Conference on Data Mining.

Early prediction of NBTI effects using RTL source code analysis

Kenneth M. Butler, Shobha Vasudevan, Jayanand Asok Kumar, 2012, DAC Design Automation Conference 2012.

Automated mapping of pre-computed module-level test sequences to processor instructions

Jacob A. Abraham, Shobha Vasudevan, S. Guramurthy, 2005, IEEE International Conference on Test, 2005..

Automated Generation and Selection of Interpretable Features for Enterprise Security

Shobha Vasudevan, Alina Oprea, Ziheng Zeng, 2018, 2018 IEEE International Conference on Big Data (Big Data).

Automatic decomposition for sequential equivalence checking of system level and RTL descriptions

Jacob A. Abraham, Shobha Vasudevan, Vinod Viswanath, 2006, Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings..

A Comparative Study of Assertion Mining Algorithms in GoldMine

Shobha Vasudevan, Lingyi Liu, Samuel Hertz, 2019 .

Mining Hardware Assertions With Guidance From Static Analysis

Shobha Vasudevan, Sam Hertz, David Sheridan, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient Microprocessor Verification using Antecedent Conditioned Slicing

Jacob A. Abraham, Shobha Vasudevan, Vinod Viswanath, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Efficient Model Checking of Hardware Using Conditioned Slicing

Jacob A. Abraham, Shobha Vasudevan, E. Allen Emerson, 2005, AVoCS.

Automatic generation of assertions from system level design using data mining

Shobha Vasudevan, Lingyi Liu, Viraj Athavale, 2011, Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011).

Scaling probabilistic timing verification of hardware using abstractions in design source code

Shobha Vasudevan, Jayanand Asok Kumar, Lingyi Liu, 2011, 2011 Formal Methods in Computer-Aided Design (FMCAD).

Code coverage of assertions using RTL source code analysis

Shobha Vasudevan, Sam Hertz, Sai Ma, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions

Shobha Vasudevan, Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Zoom Out and See Better: Scalable Message Tracing for Post-Silicon SoC Debug

Shobha Vasudevan, Debjit Pal, 2017 .

Improved verification of hardware designs through antecedent conditioned slicing

Jacob A. Abraham, Shobha Vasudevan, E. Allen Emerson, 2007, International Journal on Software Tools for Technology Transfer.

Duplex: Simultaneous parameter-performance exploration for optimizing analog circuits

Shobha Vasudevan, Seyed Nematollah Ahmadyan, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Feature Engineering for Scalable Application-Level Post-Silicon Debugging pdf

Shobha Vasudevan, Debjit Pal, Shobha Vasudevan, 2021, ArXiv.