Ganesh S. Dasika

发表

A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation

Shidhartha Das, David M. Bull, Ganesh S. Dasika, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Scalpel: Customizing DNN pruning to the underlying hardware parallelism

Scott A. Mahlke, Reetuparna Das, David J. Palframan, 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation"

David Blaauw, Krisztián Flautner, Shidhartha Das, 2011, IEEE J. Solid State Circuits.

Power-efficient medical image processing using PUMA

Scott A. Mahlke, Kevin Fan, Ganesh S. Dasika, 2009, 2009 IEEE 7th Symposium on Application Specific Processors.

A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation

David Blaauw, Krisztián Flautner, Shidhartha Das, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation

David Blaauw, Krisztián Flautner, Shidhartha Das, 2011, IEEE Journal of Solid-State Circuits.

Defining pixels to be textured

Victor W. Lee, Mikhail Smelyanskiy, Changkyu Kim, 2010 .

MEDICS: Ultra-portable processing for medical image reconstruction

Scott A. Mahlke, Trevor N. Mudge, Ankit Sethia, 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).

Erasing Core Boundaries for Robust and Configurable Performance

Amin Ansari, Shuguang Feng, Shantanu Gupta, 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation

Shidhartha Das, David M. Bull, Ganesh S. Dasika, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

PEPSC: A Power-Efficient Processor for Scientific Computing

Scott A. Mahlke, Trevor N. Mudge, Ankit Sethia, 2011, 2011 International Conference on Parallel Architectures and Compilation Techniques.

DVFS in loop accelerators using BLADES

Scott A. Mahlke, Shidhartha Das, Kevin Fan, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Increasing the number of effective registers in a low-power processor using a windowed register file

Scott A. Mahlke, Richard B. Brown, Matthew R. Guthaus, 2003, CASES '03.

Texture unit for universal computation

Victor W. Lee, Yen-Kuang Chen, Mikhail Smelyanskiy, 2010 .

Partitioning variables across register windows to reduce spill code in a low-power processor

Scott A. Mahlke, Richard B. Brown, Matthew R. Guthaus, 2005, IEEE Transactions on Computers.

Bridging the computation gap between programmable processors and hardwired accelerators

Scott A. Mahlke, Kevin Fan, Manjunath Kudlur, 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

A Customized Processor for Energy Efficient Scientific Computing

Scott A. Mahlke, Trevor N. Mudge, Ankit Sethia, 2012, IEEE Transactions on Computers.

Compiler managed dynamic instruction placement in a low-power code cache

Scott A. Mahlke, Richard B. Brown, Rajiv A. Ravindran, 2005, International Symposium on Code Generation and Optimization.

APOGEE: Adaptive prefetching on GPUs for energy efficiency

Scott A. Mahlke, Mehrzad Samadi, Ankit Sethia, 2013, Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques.

Mighty-morphing power-SIMD

Scott A. Mahlke, Trevor N. Mudge, Nathan Clark, 2010, CASES '10.

A Deep Dive Into Understanding The Random Walk-Based Temporal Graph Learning

Ronald G. Dreslinski, Danai Koutra, Trevor N. Mudge, 2021, 2021 IEEE International Symposium on Workload Characterization (IISWC).

Scalpel

David J. Palframan, Ganesh S. Dasika, S. Mahlke, 2017 .

Compressing RNNs for IoT devices by 15-38x using Kronecker Products pdf

Matthew Mattina, Igor Fedorov, Dibakar Gope, 2019, ArXiv.

BY 1538 X USING K RONECKER P RODUCTS

Jesse G. Beu, Ganesh S. Dasika, Urmish Thakker, 2020 .

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks

Yu Cao, Sarma Vrudhula, Yufei Ma, 2016, FPGA.

Power-Efficient Accelerators for High-Performance Applications

Scott Mahlke, Ganesh S. Dasika, Ganesh Dasika, 2011 .

Memory-centric system interconnect design with hybrid memory cubes

Mehrzad Samadi, Scott Mahlke, Ankit Sethia, 2013, PACT 2013.

A Deep Dive Into Understanding The Random Walk-Based Temporal Graph Learning

Trevor Mudge, Danai Koutra, Ajay Brahmakshatriya, 2021, 2021 IEEE International Symposium on Workload Characterization (IISWC).

Measuring scheduling efficiency of RNNs for NLP applications pdf

Matthew Mattina, Urmish Thakker, Jesse G. Beu, 2019, ArXiv.

Predicting room occupancy with a single passive infrared (PIR) sensor through behavior extraction

Alexis Boukouvalas, Max A. Little, Emre Ozer, 2016, UbiComp.

Ternary Hybrid Neural-Tree Networks for Highly Constrained IoT Applications pdf

Matthew Mattina, Dibakar Gope, Ganesh S. Dasika, 2019, MLSys.

BONSEYES: Platform for Open Development of Systems of Artificial Intelligence: Invited paper

Lei Wang, Kurt Tutschku, Oscar Déniz-Suárez, 2017, Conf. Computing Frontiers.

Rank and run-time aware compression of NLP Applications pdf

Matthew Mattina, Dibakar Gope, Jesse Beu, 2020, SUSTAINLP.

Compressing RNNs to Kilobyte Budget for IoT Devices Using Kronecker Products

Matthew Mattina, Igor Fedorov, Dibakar Gope, 2021, ACM J. Emerg. Technol. Comput. Syst..