Dae-Hyun Kim

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Woo-Jin Lee, Young-Hyun Jun, Jeong-Don Ihm, 2008, IEEE Journal of Solid-State Circuits.

Optimization of Channel Structures in InP HEMT Technology for Cryogenic Low-Noise and Low-Power Operation

N. Wadefalk, J. Grahn, G. Moschetti, 2023, IEEE Transactions on Electron Devices.

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process

Jang-Rae Kim, Kihan Kim, Jong-Min Bang, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

Jaehoon Jung, Chang-Kyo Lee, Hyung-Joon Chi, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

Nam Sung Kim, Chang-Kyo Lee, Hyung-Joon Chi, 2021, IEEE Journal of Solid-State Circuits.

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

Reum Oh, Byongwook Na, Jeong-Don Ihm, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).