R. Colom-Palero

Optimization of Deep Neural Networks Using SoCs with OpenCL

Rafael Gadea Gironés, Ricardo José Colom-Palero, Vicente Herrero-Bosch, 2018, Sensors.

Fast circuit topology for spatial signal distribution analysis

V. Herrero-Bosch, C. Lerche, F. Mateo-Jimenez, 2010, 2010 17th IEEE-NPSS Real Time Conference.

Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices

Marcos Martínez Peiró, Francisco José Ballester-Merelo, Rafael Gadea Gironés, 2004, Microprocess. Microsystems.

FPGA Implementation of a Pipelined On-Line Backpropagation

Rafael Gadea Gironés, Ricardo José Colom-Palero, Angel Sebastià-Cortés, 2005, J. VLSI Signal Process..

A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA

Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, 2009, 2009 International Symposium on Systems, Architectures, Modeling, and Simulation.