C. Duvvury

发表

Advanced CMOS protection device trigger mechanisms during CDM

C. Duvvury, A. Amerasekera, 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations

S. Ramaswamy, C. Duvvury, Ajith Amerasekera, 1997 .

Gate bias induced heating effect and implications for the design of deep submicron ESD protection

R.W. Dutton, C. Duvvury, Kwang-Hoon Oh, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Setting the trap for hot carriers [MOS VLSI]

C. Duvvury, S. Aur, W.R. Hunter, 1995, IEEE Circuits and Devices Magazine.

Sampling pin approaches for ESD test applications

C. Duvvury, M. Chaine, E. Grund, 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

An automated tool for detecting ESD design errors

C. Duvvury, S. Siha, H. Swaminathan, 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

ESD qualification changes for 45nm and beyond

C. Duvvury, 2008, 2008 IEEE International Electron Devices Meeting.

ESD Phenomena and Protection Issues in CMOS Output Buffers

C. Duvvury, R.N. Rountree, Y. Fong, 1987, 25th International Reliability Physics Symposium.

Integration of TLP analysis for ESD troubleshooting

C. Duvvury, J. Schichl, Li-Moum Ting, 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

EOS/ESD reliability of deep sub-micron NMOS protection devices

Sung-Mo Kang, S. Ramaswamy, C. Duvvury, 1995, Proceedings of 1995 IEEE International Reliability Physics Symposium.

Formation and suppression of a newly discovered secondary EOS event in HBM test systems

C. Duvvury, J. Schichl, T. Meuse, 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

ESD design for deep submicron SOI technology [NMOS transistor]

C. Duvvury, A. Amerasekera, S. Ramaswamy, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

Comments on "Source-and-drain series resistance of LDD MOSFET's"

C. Duvvury, D.A.G. Baglee, M.P. Duane, 1984, IEEE Electron Device Letters.

Identification of DRAM sense-amplifier imbalance using hot-carrier evaluation

C. Duvvury, S. Aur, H. McAdams, 1992 .

5-V tolerant fail-safe ESD solutions for 0.18µm logic CMOS process

C. Duvvury, H. Shichijo, K. Kunz, 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

EOS/ESD analysis of high-density logic chips

C. Duvvury, S. Ramaswamy, A. Amerasekera, 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

A PMOSFET ESD failure caused by localized charge injection

R.W. Dutton, Jung-Hoon Chun, C. Duvvury, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

IEC system level ESD challenges and effective protection strategy for USB2 interface

C. Duvvury, S. Bertonnaud, A. Jahanzeb, 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

A simulation study of HBM failure in an internal clock buffer and the design issues for efficient power pin protection strategy

C. Duvvury, V. Puvvada, 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

HBM stress of no-connect IC pins and subsequent arc-over events that lead to human-metal-discharge-like events into unstressed neighbor pins

C. Duvvury, S. Marum, J. Schichl, 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

Substrate pump NMOS for ESD protection applications

C. Duvvury, A. Amerasekera, V. Gupta, 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

Design Methodology For Optimizing Gate Driven ESD Protection Circuits In Submicron Cmos Processes

C. Duvvury, A. Amerasekera, Julian Zhiliang Chen, 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

ESD protection device issues for IC designs

C. Duvvury, 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

Design methodology of FinFET devices that meet IC-Level HBM ESD targets

R. Rooyackers, G. Groeseneken, M. Sawada, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

Latch-up in 65nm CMOS technology: a scaling perspective

C. Duvvury, V. Reddy, G. Boselli, 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

Esd in Silicon Integrated Circuits [Book Reviews]

C. Duvvury, A. Amerasekera, 1997 .

ESD: a pervasive reliability concern for IC technologies

C. Duvvury, A. Amerasekera, 1993 .

A guide to short-channel effects in MOSFETs

C. Duvvury, C. Duvvury, 1986, IEEE Circuits and Devices Magazine.

ESD and latch-up reliability for nanometer CMOS technologies

C. Duvvury, G. Boselli, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

High voltage ESD protection strategies for USB and PCI applications for 180nm/130nm/90nm CMOS technologies

C. Duvvury, R. Cline, A. Jahanzeb, 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes

C. Duvvury, E. A. Amerasekera, J. Z. Chen, 1998 .

Electrical overstress and electrostatic discharge

Sung-Mo Kang, C. Duvvury, C. Diaz, 1995 .

Lateral DMOS design for ESD robustness

C. Duvvury, D. Briggs, F. Carvajal, 1997, International Electron Devices Meeting. IEDM Technical Digest.

The impact of technology scaling on ESD robustness and protection circuit design

C. Duvvury, A. Amerasekera, A. Amerasekera, 1995 .

Statistical pin pair combinations — a new proposal for device level HBM tests

C. Duvvury, R. Gaertner, T. Brodbeck, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

Paradigm shift in ESD qualification

C. Duvvury, 2008, 2008 IEEE International Reliability Physics Symposium.

A fail-safe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 /spl mu/m CMOS I/O application

C. Duvvury, B. Haroun, J. Lin, 2002, Digest. International Electron Devices Meeting,.

The effect of high pin-count ESD tester parasitics on transiently triggered ESD clamps

C. Duvvury, L. Ting, R. Steinhoff, 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

Identification of DRAM sense amplifier imbalance using hot carrier evaluation

C. Duvvury, S. Aur, H. McAdams, 1991, 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers.

Investigation of gate to contact spacing effect on ESD robustness of salicided deep submicron single finger NMOS transistors

Kaustav Banerjee, Robert W. Dutton, C. Duvvury, 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs

Kaustav Banerjee, Robert W. Dutton, C. Duvvury, 2002 .

Single pulse CDM testing and its relevance to IC reliability

C. Duvvury, P. Koeppen, Yen-Yi Lin, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

The challenges of on-chip protection for system level cable discharge events (CDE)

C. Duvvury, Yen-Yi Lin, S. Marum, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

A new I/O signal latchup phenomenon in voltage tolerant ESD protection circuits

C. Duvvury, J. Schichl, L. Ting, 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

Dynamic gate coupling of NMOS for efficient output ESD protection

C. Duvvury, C. Diaz, C. Duvvury, 1992, 30th Annual Proceedings Reliability Physics 1992.

Drain Extended NMOS High Current Behavior and ESD Protection Strategy for HV Applications in Sub-100nm CMOS Technologies

C. Duvvury, G. Boselli, V. Vassilev, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

S. Ramaswamy, C. Duvvury, Ajith Amerasekera, 1996, Proceedings of International Reliability Physics Symposium.

FinFET current mirror design and evaluation

G. Knoblinger, A. Marshall, C. Duvvury, 2005, 2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs.

Impact of scaling on the high current behavior of RF CMOS technology

C. Duvvury, V. Reddy, G. Boselli, 2004, IEEE Transactions on Device and Materials Reliability.

Technology scaling effects on the ESD design parameters in sub-100 nm CMOS transistors

C. Duvvury, J. Rodriguez, B. Hornung, 2003, IEEE International Electron Devices Meeting 2003.

Understanding the optimization of sub-45nm FinFET devices for ESD applications

C. Duvvury, N. Collaert, D. Linten, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

ESD evaluation of the emerging MuGFET technology

A. Marshall, C. Duvvury, C.R. Cleavelin, 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

Electrical and thermal scaling trends for SOI FinFET ESD design

R. Rooyackers, C. Duvvury, N. Collaert, 2009, 2009 31st EOS/ESD Symposium.

Non-uniform conduction induced reverse channel length dependence of ESD reliability for silicided NMOS transistors

C. Duvvury, Kwang-Hoon Oh, R.W. Dutton, 2002, Digest. International Electron Devices Meeting,.

Non-uniform bipolar conduction in single finger NMOS transistors and implications for deep submicron ESD design

Kaustav Banerjee, Robert W. Dutton, C. Duvvury, 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

Unique ESD Failure Mechanism in a MuGFET Technology

C. Duvvury, H. Gossner, T. Schulz, 2006, 2006 International Electron Devices Meeting.

CDM peak current variations and impact upon CDM performance thresholds

C. Duvvury, S. Marum, J. Schichl, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Impact of Strain on ESD Robustness of FinFET Devices

R. Rooyackers, G. Meneghesso, C. Duvvury, 2008, 2008 IEEE International Electron Devices Meeting.

Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications

R. Rooyackers, C. Duvvury, N. Collaert, 2008, IEEE Transactions on Electron Devices.

Impact of Hot Carriers on Dram Circuits

C. Duvvury, H. Kitagawa, D. Redwine, 1987, 25th International Reliability Physics Symposium.