Charles J. Alpert

发表

Probability-driven routing in a datapath environment

Sachin S. Sapatnekar, Suresh Raman, Charles J. Alpert, 2002, Integr..

Keep it straight: teaching placement how to better handle designs with datapaths

Earl E. Swartzlander, David Z. Pan, Natarajan Viswanathan, 2012, ISPD '12.

Ispd2009 clock network synthesis contest

Gi-Joon Nam, Charles J. Alpert, Cliff C. N. Sze, 2009, ISPD '09.

Minimum-buffered routing of non-critical nets for slew rate and reliability control

Andrew B. Kahng, Ion I. Mandoiu, Alex Zelikovsky, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Diffusion-based placement migration

David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Techniques for Fast Physical Synthesis Fast, efficient buffer design, logic transformations, and clustering components for placement are some of the techniques being used to reduce design turnaround for large, complex chips.

Member Ieee, Charles J. Alpert, Zhuo Li, 2007 .

A fast algorithm for identifying good buffer insertion candidate locations

Charles J. Alpert, Stephen T. Quay, Milos Hrkic, 2004, ISPD '04.

Routing congestion estimation with real design constraints

Yih-Lang Li, Wen-Hao Liu, Natarajan Viswanathan, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

A two moment RC delay metric for performance optimization

Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan, 2000, ISPD '00.

Multiway partitioning via geometric embeddings, orderings, and dynamic programming

Andrew B. Kahng, Charles J. Alpert, C. Alpert, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Pyramids: An efficient computational geometry-based approach for timing-driven placement

David Z. Pan, Charles J. Alpert, Zhuo Li, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees

Derong Liu, Andrew B. Kahng, Charles J. Alpert, 2018, ISPD.

Prim-Dijkstra tradeoffs for improved performance-driven routing tree design

David R. Karger, Andrew B. Kahng, Charles J. Alpert, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm

Igor L. Markov, Gi-Joon Nam, Charles J. Alpert, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Buffer insertion with adaptive blockage avoidance

Jiang Hu, Charles J. Alpert, Stephen T. Quay, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A delay metric for RC circuits based on the Weibull distribution

Chandramouli V. Kashyap, Frank Liu, Charles J. Alpert, 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

New placement prediction and mitigation techniques for local routing congestion

Taraneh Taghavi, Shyam Ramji, Gi-Joon Nam, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Buffered Steiner trees for difficult instances

Sachin S. Sapatnekar, Charles J. Alpert, Andrew B. Kahng, 2002 .

The coming of age of physical synthesis

Charles J. Alpert, Paul G. Villarrubia, Chris Chu, 2007, ICCAD 2007.

Editorial

Narayanan Vijaykrishnan, Charles J. Alpert, Sara Dailey, 2015, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

ISPD 2005/2006 Placement Benchmarks

Gi-Joon Nam, Charles J. Alpert, Paul G. Villarrubia, 2007, Modern Circuit Placement.

Wire segmenting for improved buffer insertion

Charles J. Alpert, Anirudh Devgan, 1997, DAC.

The coming of age of physical synthesis

Chris C. N. Chu, Charles J. Alpert, Paul G. Villarrubia, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Physical Synthesis with Clock-Network Optimization for Large Systems on Chips

Igor L. Markov, Natarajan Viswanathan, Gi-Joon Nam, 2011, IEEE Micro.

CATALYST: Planning layer directives for effective design closure

Shiyan Hu, Sachin S. Sapatnekar, Charles J. Alpert, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Tutorial 3: Optimization strategies for physical synthesis and timing closure

Sachin S. Sapatnekar, Charles J. Alpert, S. Raje, 2001, ICCAD 2001.

Quantifying academic placer performance on custom designs

Earl E. Swartzlander, Charles J. Alpert, Samuel I. Ward, 2011, ISPD '11.

CRISP: Congestion reduction by iterated spreading during placement

Jarrod A. Roy, Igor L. Markov, Natarajan Viswanathan, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

MAPLE: multilevel adaptive placement for mixed-size designs

Igor L. Markov, Shyam Ramji, Natarajan Viswanathan, 2012, ISPD '12.

Placement-Driven Synthesis Design Closure Tool

Louise Trevillyan, Charles J. Alpert, Ruchir Puri, 2008, Handbook of Algorithms for Physical Design Automation.

Design-hierarchy aware mixed-size placement for routability optimization

Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Porosity-aware buffered Steiner tree construction

Jiang Hu, Charles J. Alpert, Cliff C. N. Sze, 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Buffer insertion with accurate gate and interconnect delay computation

Charles J. Alpert, Anirudh Devgan, Stephen T. Quay, 1999, DAC '99.

A general framework for vertex orderings, with applications to netlist clustering

Andrew B. Kahng, Charles J. Alpert, C. Alpert, 1994, ICCAD '94.

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

Jiang Hu, Chandramouli V. Kashyap, Chris C. N. Chu, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003

Massoud Pedram, Charles J. Alpert, C. Alpert, 2003, ACM International Symposium on Physical Design.

A place and route aware buffered Steiner tree construction

Jiang Hu, Charles J. Alpert, Cliff C. N. Sze, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees

Chandramouli V. Kashyap, Frank Liu, Charles J. Alpert, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Datapath routing based on a decongestion metric

Sachin S. Sapatnekar, Suresh Raman, Charles J. Alpert, 2000, ISPD '00.

Correction to (quote)interconnect synthesis without wire tapering(quote)

Charles J. Alpert, John P. Fishburn, Anirudh Devgan, 2002 .

Buffer insertion with adaptive blockage avoidance

Jiang Hu, Charles J. Alpert, Stephen T. Quay, 2002, ISPD '02.

Partitioning with terminals: a “new” problem and new benchmarks

Andrew B. Kahng, Igor L. Markov, Charles J. Alpert, 1999, ISPD '99.

Free space management for cut-based placement [IC layout]

Gi-Joon Nam, Charles J. Alpert, Paul G. Villarrubia, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Optimal path routing in single- and multiple-clock domain systems

Soha Hassoun, Charles J. Alpert, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Path-Based Buffer Insertion

Jiang Hu, Weiping Shi, Charles J. Alpert, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

The Effect of Free Space in Global Placement

Charles J. Alpert, Paul G. Villarrubia, Gi Jung Nam, 2002, International Conference on Computer Aided Design.

Guest editorial

Sachin S. Sapatnekar, Charles J. Alpert, Sachin S. Sapatnekar, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A faster approximation scheme for timing driven minimum cost layer assignment

Shiyan Hu, Charles J. Alpert, Zhuo Li, 2009, ISPD '09.

A semi-persistent clustering technique for VLSI circuit placement

Andrew B. Kahng, Gi-Joon Nam, Charles J. Alpert, 2005, ISPD '05.

Recent directions in netlist partitioning: a survey

Andrew B. Kahng, Charles J. Alpert, C. Alpert, 1995, Integr..

Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning

Andrew B. Kahng, Charles J. Alpert, C. Alpert, 1993, 30th ACM/IEEE Design Automation Conference.

Hippocrates: First-Do-No-Harm Detailed Placement

David Z. Pan, Gi-Joon Nam, Charles J. Alpert, 2007, 2007 Asia and South Pacific Design Automation Conference.

Shedding Physical Synthesis Area Bloat

Louise Trevillyan, Charles J. Alpert, Zhuo Li, 2011, VLSI Design.

Probabilistic Congestion Prediction with Partial Blockages

Sachin S. Sapatnekar, Weiping Shi, Charles J. Alpert, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Handbook of Algorithms for Physical Design Automation

Sachin S. Sapatnekar, Dinesh P. Mehta, Charles J. Alpert, 2008 .

Buffer insertion for noise and delay optimization

Charles J. Alpert, Anirudh Devgan, Stephen T. Quay, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

ITOP: integrating timing optimization within placement

Jarrod A. Roy, Shyam Ramji, Chris C. N. Chu, 2010, ISPD '10.

Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004

Patrick Groeneveld, Charles J. Alpert, C. Alpert, 2004 .

GLARE: Global and local wiring aware routability evaluation

Sachin S. Sapatnekar, Natarajan Viswanathan, Charles J. Alpert, 2012, DAC Design Automation Conference 2012.

Timing-driven Steiner trees are (practically) free

Andrew B. Kahng, Charles J. Alpert, Cliff C. N. Sze, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

A General Framework For Vertex Orderings, With Applications To Netlist Clustering

Andrew B. Kahng, Charles J. Alpert, C. Alpert, 1994, IEEE/ACM International Conference on Computer-Aided Design.

Modern Challenges in Constructing Clocks

Charles J. Alpert, 2017, ISPD.

A polynomial time approximation scheme for timing constrained minimum cost layer assignment

Shiyan Hu, Charles J. Alpert, Zhuo Li, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

A place and route aware buffered Steiner tree construction

Jiang Hu, Charles J. Alpert, Chin Ngai Sze, 2004 .

Practical techniques to reduce skew and its variations in buffered clock networks

Peng Li, Jiang Hu, Anand Rajaram, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Effective free space management for cut-based placement via analytical constraint generation

Gi-Joon Nam, Charles J. Alpert, Paul G. Villarrubia, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Minimum Density Interconneciton Trees

Jason Cong, Majid Sarrafzadeh, Andrew B. Kahng, 1993, ISCAS.

RQL: Global Placement via Relaxed Quadratic Spreading and Linearization

Chris C. N. Chu, Natarajan Viswanathan, Gi-Joon Nam, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Closed-form delay and slew metrics made easy

Chandramouli V. Kashyap, Frank Liu, Charles J. Alpert, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

PERI: a technique for extending delay and slew metrics to ramp inputs

Chandramouli V. Kashyap, Frank Liu, Charles J. Alpert, 2002, TAU '02.

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm

Igor L. Markov, Gi-Joon Nam, Charles J. Alpert, 2008, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A hybrid multilevel/genetic approach for circuit partitioning

Andrew B. Kahng, Charles J. Alpert, L. Hagen, 1996, Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems.

A fast hierarchical quadratic placement algorithm

Andrew B. Kahng, Gi-Joon Nam, Charles J. Alpert, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Minimum buffered routing with bounded capacitive load for slew rate and reliability control

Andrew B. Kahng, Ion I. Mandoiu, Alex Zelikovsky, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

WRIP: logic restructuring techniques for wirelength-driven incremental placement

Yu-Liang Wu, Charles J. Alpert, Cliff C. N. Sze, 2012, GLSVLSI '12.

Editorial

Narayanan Vijaykrishnan, Charles J. Alpert, Sara Dailey, 2016, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Spectral Partitioning: The More Eigenvectors, The Better

Charles J. Alpert, So-Zen Yao, C. Alpert, 1995, 32nd Design Automation Conference.

Multilevel circuit partitioning

Andrew B. Kahng, Charles J. Alpert, Dennis J.-H. Huang, 1997, DAC.

Stitch aware detailed placement for multiple e-beam lithography

David Z. Pan, Charles J. Alpert, Zhuo Li, 2016, ASP-DAC.

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

Jiang Hu, Chandramouli V. Kashyap, Chris C. N. Chu, 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

FPGA Synthesis and CAD for Reconfigurable Systems

Luca Benini, Stephen A. Edwards, Yunheung Paek, 2009 .

Steiner tree optimization for buffers. Blockages and bays

Sachin S. Sapatnekar, Jiang Hu, José Luis Neves, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

MrDP: Multiple-row detailed placement of heterogeneous-sized cells for advanced nodes

David Z. Pan, Xiaoqing Xu, Wen-Hao Liu, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Buffer insertion with accurate models for gate and interconnect delay

Charles J. Alpert, Stephen T. Quay, A. Devghan, 1999, DAC 1999.

Accurate estimation of global buffer delay within a floorplan

Sachin S. Sapatnekar, Jiang Hu, Charles J. Alpert, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Buffer insertion for noise and delay optimization

Charles J. Alpert, Anirudh Devgan, Stephen T. Quay, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Accurate estimation of global buffer delay within a floorplan

Sachin S. Sapatnekar, Jiang Hu, Charles J. Alpert, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

PACMAN: Driving Nonuniform Clock Grid Loads for low-skew robust clock network

Haifeng Qian, Charles J. Alpert, Zhuo Li, 2014, SLIP 2014.

Computational geometry based placement migration

David Z. Pan, Charles J. Alpert, Tao Luo, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Stitch aware detailed placement for multiple e-beam lithography

David Z. Pan, Charles J. Alpert, Zhuo Li, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Path-Based Buffer Insertion

Weiping Shi, Charles J. Alpert, Chin Ngai Sze, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

MULTILEVEL/GENETIC APPROACH FOR CIRCUIT PARTITIONING

Charles J. Alpert, Lars W Hagent, Andrew B. Iiahng, 1996 .

Spectral Partitioning with Multiple Eigenvectors

Andrew B. Kahng, Charles J. Alpert, So-Zen Yao, 1999, Discret. Appl. Math..

A clock distribution network for microprocessors

Keith A. Jenkins, Charles J. Alpert, Timothy G. McNamara, 2000 .

Proceedings of the 2003 international symposium on Physical design

Massoud Pedram, Charles J. Alpert, 2002 .

Diffusion-Based Placement Migration With Application on Legalization

David Z. Pan, Gi-Joon Nam, Charles J. Alpert, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Porosity-aware buffered Steiner tree construction

Jiang Hu, Charles J. Alpert, Stephen T. Quay, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Faster minimization of linear wirelength for global placement

Andrew B. Kahng, Igor L. Markov, Tony F. Chan, 1997, ISPD '97.

Is wire tapering worthwhile?

Charles J. Alpert, Anirudh Devgan, Stephen T. Quay, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Correction to "interconnect synthesis without wire tapering"

Charles J. Alpert, John P. Fishburn, Anirudh Devgan, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment

Shiyan Hu, Charles J. Alpert, Zhuo Li, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

Structure-Aware Placement Techniques for Designs With Datapaths

Earl E. Swartzlander, David Z. Pan, Natarajan Viswanathan, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Introduction to Physical Design

Sachin S. Sapatnekar, Dinesh P. Mehta, Charles J. Alpert, 2008, Handbook of Algorithms for Physical Design Automation.

A direct combination of the Prim and Dijkstra constructions for improved performance-driven global routing

Andrew B. Kahng, Charles J. Alpert, T. C. Hu, 1993, 1993 IEEE International Symposium on Circuits and Systems.

Steiner tree optimization for buffers, blockages, and bays

Sachin S. Sapatnekar, Jiang Hu, José Luis Neves, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

International Symposium on Physical Design (ISPD)

Andrew B. Kahng, Sachin S. Sapatnekar, Jiang Hu, 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Detecting tangled logic structures in VLSI netlists

Jiang Hu, Gi-Joon Nam, Charles J. Alpert, 2010, Design Automation Conference.

Analytical Engines are Unnecessary in Top-down Partitioning-based Placement

Andrew B. Kahng, Igor L. Markov, Tony F. Chan, 1999, VLSI Design.

A practical methodology for early buffer and wire resource allocation

Sachin S. Sapatnekar, Jiang Hu, Charles J. Alpert, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Optimal buffered routing path constructions for single and multiple clock domain systems

Soha Hassoun, Charles J. Alpert, Meera Thiagarajan, 2002, ICCAD 2002.

The ISPD-2011 routability-driven placement contest and benchmark suite

Jarrod A. Roy, Natarajan Viswanathan, Gi-Joon Nam, 2011, ISPD '11.

Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost

Weiping Shi, Charles J. Alpert, Zhuo Li, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Closed form expressions for extending step delay and slew metrics to ramp inputs

Chandramouli V. Kashyap, Frank Liu, Charles J. Alpert, 2003, ISPD '03.

Placement: Hot or Not?

Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A delay metric for RC circuits based on the Weibull distribution

Chandramouli V. Kashyap, Frank Liu, Charles J. Alpert, 2004, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

ICCAD-2013 CAD contest in placement finishing and benchmark suite

Natarajan Viswanathan, Charles J. Alpert, Myung-Chul Kim, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Fast Algorithms for Slew-Constrained Minimum Cost Buffering

Shiyan Hu, Jiang Hu, Weiping Shi, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

The ISPD98 circuit benchmark suite

Charles J. Alpert, C. Alpert, 1998, ISPD '98.

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths

Yu-Liang Wu, Charles J. Alpert, Cliff C. N. Sze, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Fast Electrical Correction Using Resizing and Buffering

Charles J. Alpert, Paul G. Villarrubia, Stephen T. Quay, 2007, 2007 Asia and South Pacific Design Automation Conference.

Pyramids: an efficient computational geometry-based approach for timing-driven placement

Tao Luo, David Z. Pan, Charles J. Alpert, 2008, ICCAD 2008.

Making fast buffer insertion even faster via approximation techniques

Jiang Hu, Weiping Shi, Charles J. Alpert, 2005, ASP-DAC.

What makes a design difficult to route

Jarrod A. Roy, Gi-Joon Nam, Charles J. Alpert, 2010, ISPD '10.

RC delay metrics for performance optimization

Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite

Natarajan Viswanathan, Charles J. Alpert, Zhuo Li, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Quadratic placement revisited

Igor L. Markov, Tony F. Chan, Charles J. Alpert, 1997, DAC.

Hypergraph partitioning with fixed vertices [VLSI CAD]

Andrew B. Kahng, Charles J. Alpert, Andrew E. Caldwell, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Techniques for Fast Physical Synthesis

Gi-Joon Nam, Charles J. Alpert, Zhuo Li, 2007, Proceedings of the IEEE.

Recent developments in netlist partitioning: a survey

Andrew B. Kahng, Charles J. Alpert, C. Alpert, 1995 .

A general framework for vertex orderings with applications to circuit clustering

Andrew B. Kahng, Charles J. Alpert, 1996, IEEE Trans. Very Large Scale Integr. Syst..

Free space management for cut-based placement

Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam, 2002, ICCAD 2002.

Minimum density interconnection trees

Jason Cong, Majid Sarrafzadeh, Andrew B. Kahng, 1993, 1993 IEEE International Symposium on Circuits and Systems.

An "effective" capacitance based delay metric for RC interconnect

Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Fast interconnect synthesis with layer assignment

Shiyan Hu, Charles J. Alpert, Zhuo Li, 2008, ISPD '08.

Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost

Weiping Shi, Charles J. Alpert, Zhuo Li, 2004 .

Delay and slew metrics using the lognormal distribution

Chandramouli V. Kashyap, Frank Liu, Charles J. Alpert, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

An efficient surface-based low-power buffer insertion algorithm

David Blaauw, Sani R. Nassif, Dennis Sylvester, 2005, ISPD '05.

Fast and flexible buffer trees that navigate the physical layout environment

Jiang Hu, Charles J. Alpert, Stephen T. Quay, 2004, Proceedings. 41st Design Automation Conference, 2004..

Speeding Up Physical Synthesis with Transactional Timing Analysis

Igor L. Markov, Charles J. Alpert, Michael D. Moffitt, 2010, IEEE Design & Test of Computers.

Ultra-fast interconnect driven cell cloning for minimizing critical path delay

Shiyan Hu, Weiping Shi, Charles J. Alpert, 2010, ISPD '10.

Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002

Charles J. Alpert, David P. LaPotin, John Lillis, 2002, Timing Issues in the Specification and Synthesis of Digital Systems.

A delay metric for RC circuits based on the Weibull distribution

Chandramouli V. Kashyap, Frank Liu, Charles J. Alpert, 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Techniques for scalable and effective routability evaluation

Sachin S. Sapatnekar, Natarajan Viswanathan, Charles J. Alpert, 2014, TODE.

Placement stability metrics

Gi-Joon Nam, Charles J. Alpert, Mehmet Can Yildiz, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Path smoothing via discrete optimization

Charles J. Alpert, Zhuo Li, Michael D. Moffitt, 2008, 2008 45th ACM/IEEE Design Automation Conference.

The nuts and bolts of physical synthesis

Gi-Joon Nam, Charles J. Alpert, Zhuo Li, 2007, SLIP '07.

Recent directions in netlist partitioning

Andrew B. Kahng, Charles J. Alpert, 1995 .

The ISPD2005 placement contest and benchmark suite

Gi-Joon Nam, Charles J. Alpert, Bruce Winter, 2005, ISPD '05.

A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion

Shiyan Hu, Charles J. Alpert, Zhuo Li, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Clock power minimization using structured latch templates and decision tree induction

David Z. Pan, Natarajan Viswanathan, Charles J. Alpert, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Optimal buffered routing path constructions for single and multiple clock domain systems

Soha Hassoun, Charles J. Alpert, Meera Thiagarajan, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

A practical methodology for early buffer and wire resource allocation

Sachin S. Sapatnekar, Jiang Hu, Charles J. Alpert, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Faster minimization of linear wirelength for global placement

Andrew B. Kahng, Igor L. Markov, Tony F. Chan, 1997, ISPD '97.

The DAC 2012 routability-driven placement contest and benchmark suite

Natarajan Viswanathan, Charles J. Alpert, Zhuo Li, 2012, DAC Design Automation Conference 2012.

Interconnect synthesis without wire tapering

Charles J. Alpert, John P. Fishburn, Anirudh Devgan, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

What is Physical Synthesis

Charles J. Alpert, Zhuo Li, 2011 .

Accurate estimation of global buffer delay within a floorplan

Sachin S. Sapatnekar, Jiang Hu, Charles J. Alpert, 2004, ICCAD 2004.

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing

Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, 2012, DAC Design Automation Conference 2012.

Multilevel circuit partitioning

Andrew B. Kahng, Charles J. Alpert, Dennis J.-H. Huang, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Performance-Driven Routing Tree Design

David R. Karger, Andrew B. Kahng, Charles J. Alpert, 1995 .

International Symposium on Physical Design (ISPD)

Andrew B. Kahng, Sachin S. Sapatnekar, Jiang Hu, 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A polynomial time approximation scheme for timing constrained minimum cost layer assignment

Shiyan Hu, Charles J. Alpert, Zhuo Li, 2008, ICCAD 2008.

On the Minimum Density Interconnection Tree Problem

Jason Cong, Majid Sarrafzadeh, Andrew B. Kahng, 1994 .