D. Sun

A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS

Mahmut E. Sinangil, Rawan Naous, Yih Wang, 2021, IEEE Journal of Solid-State Circuits.

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

Hidehiro Fujiwara, Tan-Li Chou, Yu-Der Chih, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations

Y. Chih, K. Akarvardar, Yih Wang, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications

Jonathan Chang, Qing Dong, Hung-Jen Liao, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies

Hidehiro Fujiwara, Jonathan Chang, Shien-Yang Wu, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications

Hidehiro Fujiwara, Jonathan Chang, Hung-Jen Liao, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM

Meng-Fan Chang, Ping Wang, Hiroyuki Yamauchi, 2012, IEEE Journal of Solid-State Circuits.