I-Chyn Wey

Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement

I-Chyn Wey, Bing-Chen Wu, Bing-Chen Wu, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block

I-Chyn Wey, Chien-Chang Peng, Feng-Yu Liao, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Pre-Computing Batch Normalisation Parameters for Edge Devices on a Binarized Neural Network

T. Teo, I-Chyn Wey, Nicholas Phipps, 2023, Sensors.

Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

I-Chyn Wey, Chun-Wei Chang, Yu-Cheng Liao, 2015, Int. J. Circuit Theory Appl..

All digital folded low‐area, low‐power maximum power point tracking chip for photovoltaic energy conversion system

I-Chyn Wey, Shu-Hao Kuo, Shu-Hao Kuo, 2014, Int. J. Circuit Theory Appl..

An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term

I-Chyn Wey, Chien-Chang Peng, Yi-Sheng Lin, 2012 .

A fast and power-saving self-timed Manchester carry-bypass adder for Booth multiplier-accumulator design

Hwang-Cherng Chow, I-Chyn Wey, You-Gang Chen, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

Fast predictive motion estimation algorithm with adaptive search mode based on motion type classification

Lili Lin, I-Chyn Wey, Jing-Hua Ding, 2014, Signal, Image and Video Processing.

Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits

I-Chyn Wey, Ye-Jhih Shen, I-Chyn Wey, 2014, Integr..

Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design

I-Chyn Wey, Chien-Chang Peng, Yi-Jung Lan, 2013, Microelectron. Reliab..